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DBLP keys2006
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electronic Testing 22(2): 161-172 (2006)
2005
5no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLOlivier Héron, Talal Arnaout, Hans-Joachim Wunderlich: On the Reliability Evaluation of SRAM-Based FPGA Designs. FPL 2005: 403-408
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electronic Testing 21(1): 43-55 (2005)
2004
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA 2004: 83-88
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS 2004: 187-192
2003
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS 2003: 124-128

Coauthor Index

1Talal Arnaout [5]
2Patrick Girard [1] [2] [3] [4] [6]
3Serge Pravossoudovitch [1] [2] [3] [4] [6]
4Michel Renovell [1] [2] [3] [4] [6]
5Hans-Joachim Wunderlich [5]

Copyright © Tue Dec 15 16:03:16 2009 by Michael Ley (ley@uni-trier.de)