Guoling Han

2008
13	EE	Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer: Exploring power management in multi-core systems. ASP-DAC 2008: 708-713
2007
12	EE	Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han: Performance modeling for early analysis of multi-core systems. CODES+ISSS 2007: 209-214
11	EE	Jason Cong, Guoling Han, Wei Jiang: Synthesis of an application-specific soft multiprocessor system. FPGA 2007: 99-107
10	EE	Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski: Accelerating Sequential Applications on CMPs Using Core Spilling. IEEE Trans. Parallel Distrib. Syst. 18(8): 1094-1107 (2007)
2006
9	EE	Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang: Behavior and communication co-optimization for systems with sequential communication media. DAC 2006: 675-678
8	EE	Jason Cong, Guoling Han, Zhiru Zhang: Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. IEEE Trans. VLSI Syst. 14(9): 986-997 (2006)
2005
7	EE	Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng: Bitwidth-aware scheduling and binding in high-level synthesis. ASP-DAC 2005: 856-861
6	EE	Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang: Instruction set extension with shadow registers for configurable processors. FPGA 2005: 99-106
5		Jason Cong, Guoling Han, Zhiru Zhang: Architecture and compilation for data bandwidth improvement in configurable embedded processors. ICCAD 2005: 263-270
2004
4	EE	Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang: Application-specific instruction generation for configurable processor architectures. FPGA 2004: 183-189
3	EE	Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang: Architecture and synthesis for on-chip multicycle communication. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 550-564 (2004)
2003
2	EE	Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang: Architecture and synthesis for multi-cycle on-chip communication. CODES+ISSS 2003: 77-78
1	EE	Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang: Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. ICCAD 2003: 536-543

Coauthor Index

1	Emrah Acar	[12]
2	Reinaldo A. Bergamaschi	[12] [13]
3	Pradip Bose	[12] [13]
4	Alper Buyuktosunoglu	[12] [13]
5	Xu Cheng	[7]
6	Jason Cong	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
7	John A. Darringer	[12] [13]
8	Nagu R. Dhanwada	[12] [13]
9	Gero Dittmann	[12] [13]
10	Yiping Fan	[1] [2] [3] [4] [6] [7] [9]
11	Zhigang Hu	[13]
12	Ashok Jagannathan	[6] [10]
13	Geert Janssen	[12] [13]
14	Wei Jiang	[9] [11]
15	Dorothy Kucar	[12]
16	Yizhou Lin	[7]
17	Indira Nair	[12] [13]
18	Gi-Joon Nam	[12]
19	Hiren D. Patel	[12] [13]
20	Glenn Reinman	[6] [10]
21	Krzysztof Rutkowski	[10]
22	Junjuan Xu	[7]
23	Xun Yang	[1] [2] [3]
24	Zhiru Zhang	[1] [2] [3] [4] [5] [6] [7] [8] [9]

Colors in the list of coauthors