Takahiro Hanyu

	2009
51		Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu: MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. DATE 2009: 433-435
50		Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet: High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving. IEICE Transactions 92-C(6): 867-874 (2009)
	2008
49		Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu: Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. ISMVL 2008: 14-19
48		Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu: High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. ISMVL 2008: 70-75
47		Hirokatsu Shirahama, Takahiro Hanyu: Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. ISMVL 2008: 8-13
46		Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu: Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling. IEICE Transactions 91-C(4): 581-588 (2008)
45		Masatomo Miura, Takahiro Hanyu: Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation. IEICE Transactions 91-C(4): 589-594 (2008)
	2007
44		Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, T. Nakamura, H. Takasu: Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic. ASP-DAC 2007: 116-117
43		Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto: Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL 2007: 43
42		Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu: Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme. ISMVL 2007: 44
41		Akira Mochizuki, Masatomo Miura, Takahiro Hanyu: High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. ISMVL 2007: 57
40		Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu: Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry. IEICE Transactions 90-C(4): 683-691 (2007)
	2006
39		Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu: Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. ISMVL 2006: 14
38		Akira Mochizuki, Takahiro Hanyu: Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. ISMVL 2006: 5
37		Takahiro Hanyu: Special Section on Novel Device Architectures and System Integration Technologies. IEICE Transactions 89-C(11): 1491 (2006)
36		Naoya Onizawa, Takahiro Hanyu: Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic. IEICE Transactions 89-C(11): 1575-1580 (2006)
35		Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu: Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic. IEICE Transactions 89-C(11): 1591-1597 (2006)
34		Tomohiro Takahashi, Takahiro Hanyu: Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing. IEICE Transactions 89-C(11): 1598-1604 (2006)
	2005
33		Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu: Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. ISMVL 2005: 138-143
32		Akira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu: TMR-Based Logic-in-Memory Circuit for Low-Power VLSI. IEICE Transactions 88-A(6): 1408-1415 (2005)
	2004
31		Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu: Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. ISMVL 2004: 192-197
30		Tomohiro Takahashi, Takahiro Hanyu: Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication. ISMVL 2004: 20-25
29		Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu: A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. ISMVL 2004: 340-345
	2003
28		Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Dynamic Source-Coupled Logic. ISMVL 2003: 207-212
27		Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama: Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. ISMVL 2003: 99-104
	2002
26		Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. ISMVL 2002: 161-
25		Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: Fully Source-Coupled Logic Based Multiple-Valued VLSI. ISMVL 2002: 270-275
	2001
24		Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, C. Zukeran: Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. ISMVL 2001: 167-172
23		Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. ISMVL 2001: 21-26
22		Takahiro Hanyu: Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI. ISMVL 2001: 241-
	2000
21		Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. ISMVL 2000: 382-
20		Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama: DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. ISMVL 2000: 423-429
19		Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama: Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. ISMVL 2000: 438-
18		Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. PRDC 2000: 27-36
	1999
17		Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1999: 275-279
16		Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama: Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. ISMVL 1999: 30-35
	1998
15		Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama: Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1998: 134-139
14		Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. ISMVL 1998: 270-275
13		Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama: Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. Systems and Computers in Japan 29(11): 40-47 (1998)
12		Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Design and evaluation of a digit-parallel multiple-valued content-addressable memory. Systems and Computers in Japan 29(11): 48-54 (1998)
	1997
11		Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama: One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1997: 175-
	1996
10		Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama: Quaternary Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1996: 224-229
9		Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu: A Multiple-Valued Ferroelectric Content-Addressable Memory. ISMVL 1996: 74-79
	1995
8		Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ISMVL 1995: 64-
7		Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama: Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. ISMVL 1995: 92-97
	1994
6		Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. ISMVL 1994: 19-26
	1993
5		Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi: A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. ISMVL 1993: 170-175
	1992
4		Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi: Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. ISMVL 1992: 274-281
	1991
3		Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi: A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. ISMVL 1991: 16-23
2		Takahiro Hanyu, Tatsuo Higuchi: A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. ISMVL 1991: 24-31
	1990
1		Takahiro Hanyu, Tatsuo Higuchi: Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. ISMVL 1990: 18-23

Coauthor Index

1	Satoshi Aragaki	[5]
2	Manabu Arakaki	[10] [11]
3	Kazutami Arimoto	[43]
4	Xiaowei Deng	[7]
5	Tetsuo Endoh	[51]
6	Vincent C. Gaudet	[50]
7	P. Glenn Gulak	[9]
8	Jun Hayakawa	[51]
9	Tatsuo Higuchi	[1] [2] [3] [4] [5]
10	Akihiro Hirosaki	[49]
11	Mitsuru Ibuki	[32]
12	Tsukasa Ike	[17] [18] [21] [23] [25]
13	Shoji Ikeda	[51]
14	Shunichi Kaeriyama	[19]
15	Michitaka Kameyama	[6] [7] [8] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [23] [24] [25] [26] [27] [28]
16	Hiromitsu Kimura	[16] [20] [26] [29] [32] [44]
17	Takeshi Kitamura	[39]
18	Yasushi Kojima	[3]
19	Atsushi Matsumoto	[49]
20	Shoun Matsunaga	[44] [51]
21	Katsuya Miura	[51]
22	Masatomo Miura	[41] [45] [49]
23	Kazuyasu Mizusawa	[42] [46]
24	Akira Mochizuki	[6] [8] [28] [31] [32] [33] [35] [38] [39] [40] [41] [43]
25	Tasuku Nagai	[48]
26	Masami Nakajima	[43]
27	T. Nakamura	[44]
28	Hideo Ohno	[51]
29	Naoya Onizawa	[33] [36] [46] [48] [50]
30	Kostas Pagiamtzis	[29]
31	Takahiro Saito	[13] [15]
32	Ali Sheikholeslami	[9] [29]
33	Katsuhiko Shimabukuro	[24]
34	Hirokatsu Shirahama	[35] [39] [40] [43] [47]
35	Tomohiro Takahashi	[27] [30] [34] [42]
36	H. Takasu	[44]
37	Kouichi Takeda	[4]
38	Takashi Takeuchi	[31]
39	Kaname Teranishi	[12] [14]
40	C. Zukeran	[24]