Masanori Hariyama

	2009
34		Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: A low-power FPGA based on autonomous fine-grain power-gating. ASP-DAC 2009: 119-120
33		Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama: An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. ERSA 2009: 145-150
32		Masanori Hariyama, Keita Tanji, Michitaka Kameyama: FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. ERSA 2009: 263-266
31		Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama: A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. ERSA 2009: 271-274
30		Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. ERSA 2009: 291-294
29		Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. IEICE Transactions 92-C(4): 539-549 (2009)
	2008
28		Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. ERSA 2008: 201-207
27		Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama: Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ERSA 2008: 309-310
26		Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama: FPGA implementation of a vehicle detection algorithm using three-dimensional information. IPDPS 2008: 1-5
25		Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. IEICE Transactions 91-A(12): 3596-3606 (2008)
24		Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama: Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. IEICE Transactions 91-C(4): 479-486 (2008)
23		Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama: Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. IEICE Transactions 91-C(4): 517-525 (2008)
22		Masanori Hariyama, Shota Ishihara, Michitaka Kameyama: Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. IEICE Transactions 91-C(9): 1419-1426 (2008)
21		Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama: Memory Allocation for Multi-Resolution Image Processing. IEICE Transactions 91-D(10): 2386-2397 (2008)
	2006
20		W. H. Muthumala, Masanori Hariyama, Michitaka Kameyama: GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. APCCAS 2006: 1264-1267
19		Masanori Hariyama, Michitaka Kameyama: A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. APCCAS 2006: 1803-1806
18		Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama: Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. IPDPS 2006
17		Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama: Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ISMVL 2006: 17
16		Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi: Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. ISVLSI 2006: 193-198
15		Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama: Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification. IEICE Transactions 89-C(11): 1551-1558 (2006)
14		Masanori Hariyama, Sho Ogata, Michitaka Kameyama: A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates. IEICE Transactions 89-C(11): 1655-1661 (2006)
	2005
13		Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama: Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. IPDPS 2005
12		Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama: Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. ISVLSI 2005: 46-50
11		Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama: Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. IEEE Trans. Computers 54(6): 642-650 (2005)
10		Weisheng Chong, Masanori Hariyama, Michitaka Kameyama: Low-Power Field-Programmable VLSI Using Multiple Supply Voltages. IEICE Transactions 88-A(12): 3298-3305 (2005)
9		Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama: FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. IEICE Transactions 88-A(12): 3516-3522 (2005)
8		Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama: Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. IEICE Transactions 88-D(7): 1486-1491 (2005)
	2004
7		Weisheng Chong, Masanori Hariyama, Michitaka Kameyama: Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. ISVLSI 2004: 243-248
6		Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama: Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. ISVLSI 2004: 258-259
	2002
5		Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama: High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. ISVLSI 2002: 95-100
	2001
4		Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama: VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. ICRA 2001: 1168-1173
	2000
3		Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama: Architecture of a high-performance stereo vision VLSI processor. Advanced Robotics 14(5): 329-332 (2000)
	1998
2		Masanori Hariyama, Michitaka Kameyama: Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. ICRA 1998: 3691-3696
	1997
1		Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama: A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. Systems and Computers in Japan 28(2): 54-61 (1997)

Coauthor Index

1	Tetsuya Aoyama	[11]
2	Yuichi Araumi	[1]
3	Weisheng Chong	[7] [10] [12] [13] [23]
4	Noriaki Idobata	[27] [31]
5	Shota Ishihara	[22] [27] [31] [33] [34]
6	Michitaka Kameyama	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34]
7	Yasuhiro Kobayashi	[9] [16] [21]
8	Yoshiya Komatsu	[33]
9	Seunghwan Lee	[3]
10	W. H. Muthumala	[20]
11	Yoshihiro Nakatani	[17] [18]
12	Sho Ogata	[12] [13] [14]
13	Naotaka Ohsawa	[5] [6]
14	Osamu Sakamoto	[6]
15	Haruka Sasaki	[8] [9]
16	Toshiki Takeuchi	[4]
17	Keita Tanji	[32]
18	Hasitha Muthumala Waidyasooriya	[23] [25] [28] [29] [30]
19	Shigeo Yamadera	[15]
20	Kensaku Yamashita	[26]
21	Naoto Yokoyama	[24]