| 2009 | ||
|---|---|---|
| 74 | Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck: SPR: an architecture-adaptive CGRA mapping tool. FPGA 2009: 191-200 | |
| 73 | Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt: FPGA-based front-end electronics for positron emission tomography. FPGA 2009: 93-102 | |
| 2008 | ||
| 72 | Kenneth Eguro, Scott Hauck: Enhancing timing-driven FPGA placement for pipelined netlists. DAC 2008: 34-37 | |
| 71 | Kenneth Eguro, Scott Hauck: Simultaneous Retiming and Placement for Pipelined Netlists. FCCM 2008: 139-148 | |
| 70 | Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck: Fpga-based data acquisition system for a positron emission tomography (PET) scanner. FPGA 2008: 264 | |
| 69 | Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert: Architectural Modifications to Enhance the Floating-Point Performance of FPGAs. IEEE Trans. VLSI Syst. 16(2): 177-187 (2008) | |
| 68 | Katherine Compton, Scott Hauck: Automatic Design of Reconfigurable Domain-Specific Flexible Cores. IEEE Trans. VLSI Syst. 16(5): 493-503 (2008) | |
| 2007 | ||
| 67 | Katherine Compton, Scott Hauck: Automatic Design of Area-Efficient Configurable ASIC Cores. IEEE Trans. Computers 56(5): 662-672 (2007) | |
| 66 | Mark Holland, Scott Hauck: Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 291-295 (2007) | |
| 2006 | ||
| 65 | Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert: Embedded floating-point units in FPGAs. FPGA 2006: 12-20 | |
| 64 | Kenneth Eguro, Scott Hauck: Armada: timing-driven pipeline-aware routing for FPGAs. FPGA 2006: 169-178 | |
| 63 | Mark Holland, Scott Hauck: Improving performance and robustness of domain-specific CPLDs. FPGA 2006: 50-59 | |
| 62 | Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert: Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs. FPL 2006: 1-6 | |
| 61 | Akshay Sharma, Carl Ebeling, Scott Hauck: PipeRoute: a pipelining-aware router for reconfigurable architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 518-532 (2006) | |
| 2005 | ||
| 60 | Kenneth Eguro, Scott Hauck, Akshay Sharma: Architecture-adaptive range limit windowing for simulated annealing FPGA placement. DAC 2005: 439-444 | |
| 59 | Michael Haselman, Michael J. Beauchamp, Aaron Wood, Scott Hauck, Keith D. Underwood, K. Scott Hemmert: A Comparison of Floating Point and Logarithmic Number Systems for FPGAs. FCCM 2005: 181-190 | |
| 58 | Shawn Phillips, Scott Hauck: Automating the Layout of Reconfigurable Subsystems Using Circuit Generators. FCCM 2005: 203-212 | |
| 57 | Mark Holland, Scott Hauck: Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. FCCM 2005: 289-290 | |
| 56 | Akshay Sharma, Carl Ebeling, Scott Hauck: Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only). FPGA 2005: 266 | |
| 55 | Akshay Sharma, Carl Ebeling, Scott Hauck: Architecture-Adaptive Routability-Driven Placement for FPGAs. FPL 2005: 427-432 | |
| 54 | Mark Holland, Scott Hauck: Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. FPL 2005: 95-100 | |
| 53 | Akshay Sharma, Scott Hauck: Accelerating FPGA Routing Using Architecture-Adaptive A* Techniques. FPT 2005: 225-232 | |
| 52 | Mark L. Chang, Scott Hauck: Précis: A Usercentric Word-Length Optimization Tool. IEEE Design & Test of Computers 22(4): 349-361 (2005) | |
| 51 | Thomas W. Fry, Scott Hauck: SPIHT image compression on FPGAs. IEEE Trans. Circuits Syst. Video Techn. 15(9): 1138-1147 (2005) | |
| 50 | Kenneth Eguro, Scott Hauck: Resource allocation for coarse-grain FPGA development. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1572-1581 (2005) | |
| 2004 | ||
| 49 | Agnieszka C. Miguel, Amanda R. Askew, Alexander Chang, Scott Hauck, Richard E. Ladner, Eve A. Riskin: Reduced Complexity Wavelet-Based Predictive Coding of Hyperspectral Images for FPGA Implementation. Data Compression Conference 2004: 469-478 | |
| 48 | Shawn Phillips, Akshay Sharma, Scott Hauck: Automating the Layout of Reconfigurable Subsystems Via Template Reduction. FCCM 2004: 340-341 | |
| 47 | Mark L. Chang, Scott Hauck: Automated Least-Significant Bit Datapath Optimization for FPGAs. FCCM 2004: 59-67 | |
| 46 | Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck: Exploration of pipelined FPGA interconnect structures. FPGA 2004: 13-22 | |
| 45 | Katherine Compton, Scott Hauck: Flexibility measurement of domain-specific reconfigurable hardware. FPGA 2004: 155-161 | |
| 44 | Mark L. Chang, Scott Hauck: Least-significant bit optimization techniques for FPGAs. FPGA 2004: 251 | |
| 43 | Mark Holland, Scott Hauck: Automatic Creation of Reconfigurable PALs/PLAs for SoC. FPL 2004: 536-545 | |
| 42 | Shawn Phillips, Akshay Sharma, Scott Hauck: Automating the Layout of Reconfigurable Subsystems via Template Reduction. FPL 2004: 857-861 | |
| 41 | Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao: The Chimaera reconfigurable functional unit. IEEE Trans. VLSI Syst. 12(2): 206-217 (2004) | |
| 2003 | ||
| 40 | Kenneth Eguro, Scott Hauck: Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development. FCCM 2003: 111-120 | |
| 39 | Katherine Compton, Scott Hauck: Track placement: orchestrating routing structures to maximize routability. FPGA 2003: 241 | |
| 38 | Akshay Sharma, Carl Ebeling, Scott Hauck: PipeRoute: a pipelining-aware router for FPGAs. FPGA 2003: 68-77 | |
| 37 | Katherine Compton, Scott Hauck: Track Placement: Orchestrating Routing Structures to Maximize Routability. FPL 2003: 121-130 | |
| 36 | Mark Holland, James Harris, Scott Hauck: Harnessing FPGAs for Computer Architecture Education. MSE 2003: 12-13 | |
| 35 | Scott Hauck: APHYDS: The Academic Physical Design Skeleton. MSE 2003: 8-9 | |
| 2002 | ||
| 34 | Mark L. Chang, Scott Hauck: Précis: A Design-Time Precision Analysis Tool. FCCM 2002: 229-238 | |
| 33 | Thomas W. Fry, Scott Hauck: Hyperspectral Image Compression on Reconfigurable Platforms. FCCM 2002: 251-260 | |
| 32 | Shawn Phillips, Scott Hauck: Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip. FPGA 2002: 165-173 | |
| 31 | Zhiyuan Li, Scott Hauck: Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. FPGA 2002: 187-195 | |
| 30 | Katherine Compton, Akshay Sharma, Shawn Phillips, Scott Hauck: Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems. FPL 2002: 59-68 | |
| 29 | Katherine Compton, Scott Hauck: Reconfigurable computing: a survey of systems and software. ACM Comput. Surv. 34(2): 171-210 (2002) | |
| 28 | Katherine Compton, Zhiyuan Li, James Cooley, Stephen Knol, Scott Hauck: Configuration relocation and defragmentation for run-time reconfigurable computing. IEEE Trans. VLSI Syst. 10(3): 209-220 (2002) | |
| 2001 | ||
| 27 | Sinan Kaptanoglu, John East, Tim Garverick, Scott Hauck, Tavana Tavana, Steven Trimberger, Ronnie Vasishta: Is marriage in the cards for programmable logic, microprocessors and ASICs? FPGA 2001: 111 | |
| 26 | Chandra Mulpuri, Scott Hauck: Runtime and quality tradeoffs in FPGA placement and routing. FPGA 2001: 29-36 | |
| 2000 | ||
| 25 | Zhiyuan Li, Katherine Compton, Scott Hauck: Configuration Caching Management Techniques for Reconfigurable Computing. FCCM 2000: 22-38 | |
| 24 | Katherine Compton, James Cooley, Stephen Knol, Scott Hauck: Configuration Relocation and Defragmentation for Reconfigurable Computing. FCCM 2000: 279-280 | |
| 23 | Prithviraj Banerjee, U. Nagaraj Shenoy, Alok N. Choudhary, Scott Hauck, C. Bachmann, Malay Haldar, Pramod G. Joisha, Alex K. Jones, Abhay Kanhere, Anshuman Nayak, S. Periyacheri, M. Walkden, David Zaretsky: A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems. FCCM 2000: 39-48 | |
| 22 | Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee: CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. ISCA 2000: 225-235 | |
| 21 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry: High-performance carry chains for FPGA's. IEEE Trans. VLSI Syst. 8(2): 138-147 (2000) | |
| 1999 | ||
| 20 | Scott Hauck, William D. Wilson: Runlength Compression Techniques for FPGA Configurations. FCCM 1999: 286- | |
| 19 | Zhiyuan Li, Scott Hauck: Don't Care Discovery for FPGA Configuration Compression. FPGA 1999: 91-98 | |
| 18 | Scott Hauck, Zhiyuan Li, Eric J. Schwabe: Configuration compression for the Xilinx XC6200 FPGA. IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1107-1113 (1999) | |
| 17 | Morgan Enos, Scott Hauck, Majid Sarrafzadeh: Evaluation and optimization of replication algorithms for logic bipartitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1237-1248 (1999) | |
| 1998 | ||
| 16 | Scott Hauck, Stephen Knol: Data Security for Web-based CAD. DAC 1998: 788-793 | |
| 15 | Scott Hauck, Zhiyuan Li, Eric J. Schwabe: Configuration Compression for the Xilinx XC6200 FPGA. FCCM 1998: 138-146 | |
| 14 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry: High-Performance Carry Chains for FPGAs. FPGA 1998: 223-233 | |
| 13 | Scott Hauck: Configuration Prefetch for Single Context Reconfigurable Coprocessors. FPGA 1998: 65-74 | |
| 12 | Scott Hauck, Gaetano Borriello, Carl Ebeling: Mesh routing topologies for multi-FPGA systems. IEEE Trans. VLSI Syst. 6(3): 400-408 (1998) | |
| 1997 | ||
| 11 | Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao: The Chimaera reconfigurable functional unit. FCCM 1997: 87-97 | |
| 10 | Morgan Enos, Scott Hauck, Majid Sarrafzadeh: Replication for logic bipartitioning. ICCAD 1997: 342-349 | |
| 9 | Scott Hauck, Gaetano Borriello: An evaluation of bipartitioning techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 849-866 (1997) | |
| 8 | Scott Hauck, Gaetano Borriello: Pin assignment for multi-FPGA systems. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 956-964 (1997) | |
| 1995 | ||
| 7 | Scott Hauck, Gaetano Borriello: An evaluation of bipartitioning techniques. ARVLSI 1995: 383-403 | |
| 6 | Scott Hauck, Gaetano Borriello: Logic Partition Orderings for Multi-FPGA Systems. FPGA 1995: 32-38 | |
| 5 | Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns: Placement and routing tools for the Triptych FPGA. IEEE Trans. VLSI Syst. 3(4): 473-482 (1995) | |
| 4 | Gaetano Borriello, Carl Ebeling, Scott Hauck, Steven M. Burns: The Triptych FPGA architecture. IEEE Trans. VLSI Syst. 3(4): 491-501 (1995) | |
| 1994 | ||
| 3 | Scott Hauck, Gaetano Borriello, Carl Ebeling: Mesh Routing Topologies for Multi-FPGA Systems. ICCD 1994: 170-177 | |
| 2 | Scott Hauck, Steven M. Burns, Gaetano Borriello, Carl Ebeling: An FPGA for Implementing Asynchronous Circuits. IEEE Design & Test of Computers 11(3): 60-69 (1994) | |
| 1992 | ||
| 1 | Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling: MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. FPL 1992: 44-51 | |