 | 2008 |
|---|
| 6 |       | Zhiyong He,
Kerong Ben,
Zhixiang Zhang:
Software Architectural Reflection Mechanism for Runtime Adaptation.
ICYCS 2008: 1101-1105 |
| 2007 |
|---|
| 5 | | Zhiyong He,
Sébastien Roy,
Paul Fortier:
Lowering Error Floor of LDPC Codes Using a Joint Row-Column Decoding Algorithm.
ICC 2007: 920-925 |
| 4 | | Zhiyong He,
Sébastien Roy,
Paul Fortier:
FPGA Implementation of LDPC Decoders Based on Joint Row-column Decoding Algorithm.
ISCAS 2007: 1653-1656 |
| 2006 |
|---|
| 3 | | Zhiyong He,
Sébastien Roy,
Paul Fortier:
Encoder architecture with throughput over 10 Gbit/sec for quasi-cyclic LDPC codes.
ISCAS 2006 |
| 2 | | Zhiyong He,
Paul Fortier,
Sébastien Roy:
Highly-Parallel Decoding Architectures for Convolutional Turbo Codes.
IEEE Trans. VLSI Syst. 14(10): 1147-1151 (2006) |
| 2005 |
|---|
| 1 | | Zhiyong He,
Sébastien Roy,
Paul Fortier:
High-speed and low-power design of parallel turbo decoder.
ISCAS (6) 2005: 6018-6021 |
