 | 2009 |
|---|
| 10 |       | J. Robert Heath,
Nien Y. Lim,
Kenneth L. Calvert,
Jim Griffioen:
A New Reconfigurable Network Node Processor Architecture for Distributed Implementation of Ephemeral State Processing.
ISCA PDCCS 2009: 213-220 |
| 9 | | J. Robert Heath,
Sridhar Hegde,
Kanchan Bhide:
Development and Validation of a Load Balancing and Control Mechanism for a Reconfigurable Single-Chip Heterogenous and Hybrid Multiprocessor Architecture Platform.
ISCA PDCCS 2009: 228-235 |
| 2001 |
|---|
| 8 |  | J. Robert Heath,
Andrew Tan:
Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture.
IEEE International Workshop on Rapid System Prototyping 2001: 128-135 |
| 1994 |
|---|
| 7 | | Tae Won Cho,
Sam S. Pyo,
J. Robert Heath:
PARALLEX: a parallel approach to switchbox routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 684-693 (1994) |
| 1984 |
|---|
| 6 | | George Broomell,
J. Robert Heath:
An Integrated-Circuit Crossbar Switching System Design.
ICDCS 1984: 278-287 |
| 1983 |
|---|
| 5 | | George Broomell,
J. Robert Heath:
Classification Categories and Historical Development of Circuit Switching Topologies.
ACM Comput. Surv. 15(2): 95-133 (1983) |
| 1982 |
|---|
| 4 | | Andrew D. Hurt,
J. Robert Heath:
The Design of a Fault-Tolerant Computing Element for Distributed Data Processors.
ICDCS 1982: 171-176 |
| 3 | | J. Robert Heath,
George Broomell,
Andrew D. Hurt:
A distributed computer architecture for real-time, data driven applications.
ICDCS 1982: 630-638 |
| 2 | | Andrew D. Hurt,
J. Robert Heath:
A Hardware Task Scheduling Mechanism for a Real-Time Multi-Microprocessor Architecture.
IEEE Real-Time Systems Symposium 1982: 113-123 |
| 1980 |
|---|
| 1 | | J. Robert Heath,
James Cline:
The Complexity and Use of a Multistage Interconnection Network for Distributed Processing Systems.
IEEE Real-Time Systems Symposium 1980: 28-35 |
