Hiroomi Hikawa

	2009
18		Seiji Miyoshi, Hiroomi Hikawa, Yutaka Maeda: Statistical Mechanical Analysis of Simultaneous Perturbation Learning. IEICE Transactions 92-A(7): 1743-1746 (2009)
	2008
17		Hiroomi Hikawa, Hirotada Fujimura: Hardware Design of Japanese Hand Sign Recognition System. ICONIP (2) 2008: 835-842
	2007
16		Hirotada Fujimura, Yuuichi Sakai, Hiroomi Hikawa: Japanese Hand Sign Recognition System. ICONIP (1) 2007: 983-992
15		Hiroomi Hikawa, Kaori Kugimiya: A New Hardware Friendly Vector Distance Evaluation Function for Vector Classifiers. ICONIP (2) 2007: 137-146
14		Hiroomi Hikawa, Shigeki Matsubara: Pseudo RBF Network for Position Independent Hand Posture Recognition System. IJCNN 2007: 1049-1054
13		Hiroomi Hikawa, Taku Miyanishi, Kousuke Tamaya: Performance Comparison of SOM Based Hybrid Hardware Classifiers. IJCNN 2007: 1091-1096
12		Hiroomi Hikawa, Kazutoshi Harada, Takenori Hirabayashi: Hardware Feedback Self-Organizing Map and its Application to Mobile Robot Location Identification. JACIII 11(8): 937-945 (2007)
	2006
11		Hiroomi Hikawa: Vector Quantization System Based on Scalar SOM/AND-OR Hybrid Network. IJCNN 2006: 1489-1496
	2005
10		Hiroomi Hikawa: FPGA implementation of self organizing map with digital phase locked loops. Neural Networks 18(5-6): 514-522 (2005)
	2004
9		Hiroomi Hikawa: Direct digital frequency synthesizer with multi-stage linear interpolation. ISCAS (4) 2004: 233-236
	2003
8		Hiroomi Hikawa: Pulse mode neuron with leakage integrator and additive random noise. ISCAS (5) 2003: 821-824
7		Hiroomi Hikawa: A multilayer neural network with pulse position modulation. Systems and Computers in Japan 34(13): 36-46 (2003)
	2000
6		Hiroomi Hikawa: Pulse Mode Multilayer Neural Network with Floating Point Operation and On-Chip Learning. IJCNN (2) 2000: 71-80
5		Hiroomi Hikawa: An efficient three-valued multilayer neural network with on-chip learning suitable for hardware implementation. Systems and Computers in Japan 31(4): 43-51 (2000)
	1999
4		Hiroomi Hikawa: An efficient pulse mode multilayer neural network. ISCAS (5) 1999: 367-370
	1994
3		Vijay K. Jain, Hiroomi Hikawa: Parallel Architecture for Universal Digital Signal Processing. HICSS (1) 1994: 114-123
	1992
2		Vijay K. Jain, Hiroomi Hikawa, David C. Keezer: An Architecture for WSI Rapid Prototyping. IEEE Computer 25(4): 71-75 (1992)
1		Earl E. Swartzlander Jr., Vijay K. Jain, Hiroomi Hikawa: A radix-8 wafer scale FFT processor. VLSI Signal Processing 4(2-3): 165-176 (1992)

Coauthor Index

1	Hirotada Fujimura	[16] [17]
2	Kazutoshi Harada	[12]
3	Takenori Hirabayashi	[12]
4	Vijay K. Jain	[1] [2] [3]
5	David C. Keezer	[2]
6	Kaori Kugimiya	[15]
7	Yutaka Maeda	[18]
8	Shigeki Matsubara	[14]
9	Taku Miyanishi	[13]
10	Seiji Miyoshi	[18]
11	Yuuichi Sakai	[16]
12	Earl E. Swartzlander Jr.	[1]
13	Kousuke Tamaya	[13]

Colors in the list of coauthors