Akio Hirata

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1998

1 Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru: Proposal of a timing model for CMOS logic gates driving a CRC load. ICCAD 1998: 537-544

	1998
1		Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru: Proposal of a timing model for CMOS logic gates driving a CRC load. ICCAD 1998: 537-544

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