Andrzej Hlawiczka

	2009
20		Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka: Effective BIST for crosstalk faults in interconnects. DDECS 2009: 164-169
	2008
19		Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec: Interconnect Faults Identification and Localization Using Modified Ring LFSRs. DDECS 2008: 247-250
	2007
18		Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka: Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. DDECS 2007: 149-152
17		Tomasz Rudnicki, Andrzej Hlawiczka: Test Pattern Generator for Delay Faults. DDECS 2007: 255-258
	2006
16		Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka: Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. DDECS 2006: 230-231
15		Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka: Test-per-Clock Detection, Localization and Identification of Interconnect Faults. European Test Symposium 2006: 233-238
	2004
14		Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa: Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. J. Electronic Testing 20(1): 109-122 (2004)
	2002
13		Tomasz Garbolino, Andrzej Hlawiczka: Efficient test pattern generators based on specific cellular automata structures. Microelectronics Reliability 42(6): 975-983 (2002)
	2000
12		Andrzej Hlawiczka, Michal Kopec: Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata. Asian Test Symposium 2000: 380-385
	1999
11		Tomasz Garbolino, Andrzej Hlawiczka: A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits. EDCC 1999: 321-338
	1997
10		Dariusz Badura, Andrzej Hlawiczka: Low Cost Bist for Edac Circuits. Asian Test Symposium 1997: 410-415
9		Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan: A linear code-preserving signature analyzer COPMISR. VTS 1997: 350-355
	1996
8		Andrzej Hlawiczka, João Gabriel Silva, Luca Simoncini: Dependable Computing - EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 1996, Proceedings Springer 1996
	1994
7		Andrzej Hlawiczka, Jacek Binda: Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures. FPL 1994: 120-122
	1992
6		Andrzej Hlawiczka: Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks. IEEE Trans. Computers 41(12): 1562-1571 (1992)
	1989
5		Andrzej Hlawiczka: Signature Analysis Testing with Bottom-Top Exclusive Or Type MISR. Fehlertolerierende Rechensysteme 1989: 356-367
	1987
4		Andrzej Hlawiczka, Dariusz Badura: Universal Test Controller Chip for Board Self Test. Fehlertolerierende Rechensysteme 1987: 165-175
	1986
3		Andrzej Hlawiczka: Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer. IEEE Trans. Computers 35(8): 732-741 (1986)
	1984
2		Andrzej Hlawiczka: Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzer. Fehlertolerierende Rechensysteme 1984: 404-416
	1978
1		Andrzej Hlawiczka: Comments on `` Procedures for Eliminating Static and Dynamic-Hazards in Test Generation''. IEEE Trans. Computers 27(2): 191 (1978)

Coauthor Index

1	Dariusz Badura	[4] [10]
2	Jacek Binda	[7]
3	Tomasz Garbolino	[11] [13] [14] [15] [16] [18] [19] [20]
4	Michael Gössel	[9]
5	Krzysztof Gucwa	[14] [15] [16] [18] [19] [20]
6	Michal Kopec	[12] [15] [16] [18] [19]
7	Jiri Nosek	[14]
8	Ondrej Novák	[14]
9	Zdenek Plíva	[14]
10	Tomasz Rudnicki	[17] [20]
11	João Gabriel Silva	[8]
12	Luca Simoncini	[8]
13	Egor S. Sogomonyan	[9]

Colors in the list of coauthors