 | 2009 |
|---|
| 12 |       | Richard F. Hobson:
A 5T Sram Cell with 4 Power Terminals for Read/Write/Standby Assist.
CDES 2009: 10-16 |
| 2007 |
|---|
| 11 |  | Richard F. Hobson:
A New Single-Ended SRAM Cell With Write-Assist.
IEEE Trans. VLSI Syst. 15(2): 173-181 (2007) |
| 2004 |
|---|
| 10 | | Richard F. Hobson,
Allan R. Dyck,
Keith Cheung:
SoC Features for a Multi-Processor WCDMA Base-station Modem.
IWSOC 2004: 318-321 |
| 1999 |
|---|
| 9 | | Richard F. Hobson,
Allan R. Dyck:
A Multiple-Input Single-Phase Clock Flip-Flop Family.
Great Lakes Symposium on VLSI 1999: 240-241 |
| 8 | | R. Balakrishnan,
Richard F. Hobson:
A Greedy Router with Technology Targetable Output.
Great Lakes Symposium on VLSI 1999: 252-255 |
| 7 | | Allan R. Dyck,
S. Evenson,
H. Fu,
Richard F. Hobson:
User selectable feature support for an embedded processor.
ISCAS (1) 1999: 9-12 |
| 6 | | Richard F. Hobson,
P. S. Wong:
A parallel embedded-processor architecture for ATM reassembly.
IEEE/ACM Trans. Netw. 7(1): 23-37 (1999) |
| 1998 |
|---|
| 5 | | Richard F. Hobson:
Power Reducing Techniques for Clocked CMOS PLAs.
Great Lakes Symposium on VLSI 1998: 34-38 |
| 1989 |
|---|
| 4 | | Richard F. Hobson,
J. D. Hoskin,
R. W. Spilsbury:
Opportunities for System and User Features in a New APL Interpreter.
APL 1989: 190-196 |
| 1984 |
|---|
| 3 | | Richard F. Hobson:
A Directly Executable Encoding for APL.
ACM Trans. Program. Lang. Syst. 6(3): 314-332 (1984) |
| 1981 |
|---|
| 2 | | Richard F. Hobson:
Software sympathetic chip set design.
AFIPS National Computer Conference 1981: 3-10 |
| 1 | | Richard F. Hobson:
Structured Machine Design: An Ongoing Experiement.
ISCA 1981: 37-56 |
