M. Hollreiser

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1995

1 Giuseppe Caire, Javier Ventura-Traveset, M. Hollreiser, Ezio Biglieri: Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers. VLSI Signal Processing 10(2): 153-168 (1995)

	1995
1		Giuseppe Caire, Javier Ventura-Traveset, M. Hollreiser, Ezio Biglieri: Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers. VLSI Signal Processing 10(2): 153-168 (1995)

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