 | 2009 |
|---|
| 10 |       | Avesta Sasan,
Houman Homayoun,
Ahmed M. Eltawil,
Fadi J. Kurdahi:
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).
CASES 2009: 251-260 |
| 9 | | Avesta Sasan,
Houman Homayoun,
Ahmed M. Eltawil,
Fadi J. Kurdahi:
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling.
DATE 2009: 911-916 |
| 2008 |
|---|
| 8 | | Houman Homayoun,
Mohammad A. Makhzan,
Alexander V. Veidenbaum:
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors.
CASES 2008: 197-206 |
| 7 | | Houman Homayoun,
Sudeep Pasricha,
Mohammad A. Makhzan,
Alexander V. Veidenbaum:
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.
DAC 2008: 68-71 |
| 6 | | Houman Homayoun,
Alexander V. Veidenbaum,
Jean-Luc Gaudiot:
Adaptive techniques for leakage power management in L2 cache peripheral circuits.
ICCD 2008: 563-569 |
| 5 | | Houman Homayoun,
Mohammad A. Makhzan,
Alexander V. Veidenbaum:
ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.
ICCD 2008: 699-706 |
| 4 | | Houman Homayoun,
Sudeep Pasricha,
Mohammad A. Makhzan,
Alexander V. Veidenbaum:
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors.
LCTES 2008: 71-78 |
| 2007 |
|---|
| 3 | | Houman Homayoun,
Alexander V. Veidenbaum:
Reducing leakage power in peripheral circuits of L2 caches.
ICCD 2007: 230-237 |
| 2006 |
|---|
| 2 | | Houman Homayoun,
Ted H. Szymanski:
Reducing the Instruction Queue Leakage Power in Superscalar Processors.
CCECE 2006: 1685-1689 |
| 1 | | Houman Homayoun,
Amirali Baniasadi:
Reducing Execution Unit Leakage Power in Embedded Processors.
SAMOS 2006: 299-308 |
