Naofumi Homma

2008
23	EE	Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki: High-Performance Concurrent Error Detection Scheme for AES Hardware. CHES 2008: 100-112
22	EE	Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir: Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs. CHES 2008: 15-29
21	EE	Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi: High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. ISMVL 2008: 112-117
20	EE	Naofumi Homma, Sei Nagashima, Takeshi Sugawara, Takafumi Aoki, Akashi Satoh: A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks. IEICE Transactions 91-A(1): 193-202 (2008)
2007
19	EE	Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi: Application of symbolic computer algebra to arithmetic circuit verification. ICCD 2007: 25-32
18	EE	Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh: DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. ISCAS 2007: 1807-1810
17	EE	Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh: SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. ISCAS 2007: 1847-1850
16	EE	Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh: A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. ISCAS 2007: 1859-1862
15	EE	Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi: Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. ISMVL 2007: 31
2006
14	EE	Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh: High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. CHES 2006: 187-200
13	EE	Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi: Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic. ISMVL 2006: 2
12	EE	Naofumi Homma, Yuki Watanabe, Takafumi Aoki, Tatsuo Higuchi: Formal Design of Arithmetic Circuits Based on Arithmetic Description Language. IEICE Transactions 89-A(12): 3500-3509 (2006)
11	EE	Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi: Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic. IEICE Transactions 89-C(11): 1645-1654 (2006)
2004
10	EE	Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi: Multiplier Block Synthesis Using Evolutionary Graph Generation. Evolvable Hardware 2004: 79-82
9		Naofumi Homma, Jun Sakiyama, Taihei Wakamatsu, Takafumi Aoki, Tatsuo Higuchi: A systematic approach for analyzing fast addition algorithms using counter tree diagrams. ISCAS (5) 2004: 197-200
8	EE	Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi: Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH. ISMVL 2004: 334-339
7	EE	Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi: Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation. PPSN 2004: 342-351
2003
6	EE	Naofumi Homma, Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi: VLSI circuit design using an object-oriented framework of evolutionary graph generation system. IEEE Congress on Evolutionary Computation (1) 2003: 115-122
5	EE	Naofumi Homma, Takafumi Aoki, Makoto Motegi, Tatsuo Higuchi: A framework of evolutionary graph generation system and its application to circuit synthesis. ISCAS (5) 2003: 201-204
4	EE	Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi: Evolutionary Synthesis of Arithmetic Circuit Structures. Artif. Intell. Rev. 20(3-4): 199-232 (2003)
2002
3	EE	Makoto Motegi, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi: Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis. PPSN 2002: 831-840
2		Dingjun Chen, Takafumi Aoki, Naofumi Homma, Toshiki Terasaki, Tatsuo Higuchi: Graph-based evolutionary design of arithmetic circuits. IEEE Trans. Evolutionary Computation 6(1): 86-100 (2002)
2001
1	EE	Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi: Evolutionary graph generation system with transmigration capability for arithmetic circuit design. ISCAS (5) 2001: 171-174

Coauthor Index

1	Takafumi Aoki	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23]
2	Dingjun Chen	[2]
3	Katsuhiko Degawa	[15] [21]
4	Tatsuo Higuchi	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [15] [19] [21]
5	Yuichi Imai	[14] [18]
6	Kazuya Ishida	[8]
7	Atsushi Miyamoto	[17] [22]
8	Makoto Motegi	[3] [5]
9	Sei Nagashima	[14] [18] [20]
10	Masanori Natsui	[6] [7]
11	Jun Sakiyama	[9]
12	Akashi Satoh	[14] [16] [17] [18] [20] [22] [23]
13	Adi Shamir	[22]
14	Takeshi Sugawara	[16] [20] [23]
15	Toshiki Terasaki	[2]
16	Taihei Wakamatsu	[9]
17	Yuki Watanabe	[12] [19] [21]