| 2008 |
|---|
| 194 | EE | Liangpeng Guo,
Yici Cai,
Qiang Zhou,
Le Kang,
Xianlong Hong:
A novel performance driven power gating based on distributed sleep transistor network.
ACM Great Lakes Symposium on VLSI 2008: 255-260 |
| 193 | EE | Xin Li,
Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Jason Cong:
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.
ASP-DAC 2008: 209-212 |
| 192 | EE | Yanfeng Wang,
Qiang Zhou,
Yici Cai,
Jiang Hu,
Xianlong Hong,
Jinian Bian:
Low power clock buffer planning methodology in F-D placement for large scale circuit design.
ASP-DAC 2008: 370-375 |
| 191 | EE | Xiaoyi Wang,
Jin Shi,
Yici Cai,
Xianlong Hong:
Heuristic power/ground network and floorplan co-design method.
ASP-DAC 2008: 617-622 |
| 190 | EE | Shuai Li,
Jin Shi,
Yici Cai,
Xianlong Hong:
Vertical via design techniques for multi-layered P/G networks.
ASP-DAC 2008: 623-628 |
| 189 | EE | Jiayi Liu,
Sheqin Dong,
Xianlong Hong,
Yibo Wang,
Ou He,
Satoshi Goto:
Symmetry constraint based on mismatch analysis for analog layout in SOI technology.
ASP-DAC 2008: 772-775 |
| 188 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu:
Activity and register placement aware gated clock network design.
ISPD 2008: 182-189 |
| 187 | EE | Haixia Yan,
Qiang Zhou,
Xianlong Hong:
Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm.
ISQED 2008: 289-292 |
| 186 | EE | Yin Shen,
Yici Cai,
Qiang Zhou,
Xianlong Hong:
DFM Based Detailed Routing Algorithm for ECP and CMP.
ISQED 2008: 357-360 |
| 185 | EE | Xiang Qiu,
Yuchun Ma,
Xiangqing He,
Xianlong Hong:
IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization.
ISQED 2008: 873-876 |
| 184 | EE | Yanming Jia,
Yici Cai,
Xianlong Hong:
Full-chip routing system for reducing Cu CMP & ECP variation.
SBCCI 2008: 10-15 |
| 183 | EE | Zhen Cao,
Tong T. Jing,
Jinjun Xiong,
Yu Hu,
Zhe Feng,
Lei He,
Xianlong Hong:
Fashion: A Fast and Accurate Solution to Global Routing Problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 726-737 (2008) |
| 182 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu:
Low Power Gated Clock Tree Driven Placement.
IEICE Transactions 91-A(2): 595-603 (2008) |
| 181 | EE | Liangpeng Guo,
Yici Cai,
Qiang Zhou,
Xianlong Hong:
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage.
IEICE Transactions 91-A(8): 2084-2090 (2008) |
| 180 | EE | Yici Cai,
Jin Shi,
Zhu Pan,
Xianlong Hong,
Sheldon X.-D. Tan:
Large scale P/G grid transient simulation using hierarchical relaxed approach.
Integration 41(1): 153-160 (2008) |
| 179 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu,
Bing Lu:
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.
Integration 41(3): 426-438 (2008) |
| 178 | EE | Yici Cai,
Qiang Zhou,
Xianlong Hong,
Rui Shi,
Yang Wang:
Application of optical proximity correction technology.
Science in China Series F: Information Sciences 51(2): 213-224 (2008) |
| 2007 |
|---|
| 177 | EE | Yanming Jia,
Yici Cai,
Xianlong Hong:
Dummy fill aware buffer insertion during routing.
ACM Great Lakes Symposium on VLSI 2007: 31-36 |
| 176 | EE | Xinjie Wei,
Yici Cai,
Xianlong Hong:
Physical aware clock skew rescheduling.
ACM Great Lakes Symposium on VLSI 2007: 473-476 |
| 175 | EE | Ou He,
Sheqin Dong,
Jinian Bian,
Yuchun Ma,
Xianlong Hong:
An effective buffer planning algorithm for IP based fixed-outline SOC placement.
ACM Great Lakes Symposium on VLSI 2007: 564-569 |
| 174 | EE | Yue Zhuo,
Hao Li,
Qiang Zhou,
Yici Cai,
Xianlong Hong:
New timing and routability driven placement algorithms for FPGA synthesis.
ACM Great Lakes Symposium on VLSI 2007: 570-575 |
| 173 | EE | Jiayi Liu,
Sheqin Dong,
Yuchun Ma,
Di Long,
Xianlong Hong:
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation.
ASP-DAC 2007: 191-196 |
| 172 | EE | Zhen Cao,
Tong Jing,
Jinjun Xiong,
Yu Hu,
Lei He,
Xianlong Hong:
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.
ASP-DAC 2007: 256-261 |
| 171 | EE | Yi Zou,
Yici Cai,
Qiang Zhou,
Xianlong Hong,
Sheldon X.-D. Tan,
Le Kang:
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.
ASP-DAC 2007: 367-372 |
| 170 | EE | Liangpeng Guo,
Yici Cai,
Qiang Zhou,
Xianlong Hong:
Logic and Layout Aware Voltage Island Generation for Low Power Design.
ASP-DAC 2007: 666-671 |
| 169 | EE | Le Kang,
Yici Cai,
Yi Zou,
Jin Shi,
Xianlong Hong,
Sheldon X.-D. Tan:
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.
ASP-DAC 2007: 751-756 |
| 168 | EE | Yuchun Ma,
Zhuoyuan Li,
Jason Cong,
Xianlong Hong,
Glenn Reinman,
Sheqin Dong,
Qiang Zhou:
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.
ASP-DAC 2007: 920-925 |
| 167 | EE | Jeffrey Fan,
Ning Mi,
Sheldon X.-D. Tan,
Yici Cai,
Xianlong Hong:
Statistical model order reduction for interconnect circuits considering spatial correlations.
DATE 2007: 1508-1513 |
| 166 | EE | Ning Mi,
Sheldon X.-D. Tan,
Pu Liu,
Jian Cui,
Yici Cai,
Xianlong Hong:
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks.
ICCAD 2007: 48-53 |
| 165 | EE | Pingqiang Zhou,
Yuchun Ma,
Zhuoyuan Li,
Robert P. Dick,
Li Shang,
Hai Zhou,
Xianlong Hong,
Qiang Zhou:
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.
ICCAD 2007: 590-597 |
| 164 | EE | Xinjie Wei,
Yici Cai,
Xianlong Hong:
Effective Acceleration of Iterative Slack Distribution Process.
ISCAS 2007: 1077-1080 |
| 163 | EE | Yanfeng Wang,
Qiang Zhou,
Xianlong Hong,
Yici Cai:
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.
ISCAS 2007: 2040-2043 |
| 162 | EE | Lingyi Zhang,
Sheqin Dong,
Xianlong Hong,
Yuchun Ma:
A Fast 3D-BSG Algorithm for 3D Packing Problem.
ISCAS 2007: 2044-2047 |
| 161 | EE | Haixia Yan,
Zhuoyuan Li,
Xianlong Hong,
Qiang Zhou:
Unified Quadratic Programming Approach For 3-D Mixed Mode Placement.
ISCAS 2007: 3411-3414 |
| 160 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu,
Bing Lu:
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.
ISQED 2007: 299-304 |
| 159 | EE | Yici Cai,
Bin Liu,
Jin Shi,
Qiang Zhou,
Xianlong Hong:
Power Delivery Aware Floorplanning for Voltage Island Designs.
ISQED 2007: 350-355 |
| 158 | EE | Hongjie Bai,
Sheqin Dong,
Xianlong Hong:
Congestion Driven Buffer Planning for X-Architecture.
ISQED 2007: 835-840 |
| 157 | EE | Liu Yang,
Sheqin Dong,
Yuchun Ma,
Xianlong Hong:
Interconnect Power Optimization Based on Timing Analysis.
ISVLSI 2007: 119-124 |
| 156 | EE | Hailong Yao,
Yici Cai,
Xianlong Hong:
CMP-aware Maze Routing Algorithm for Yield Enhancement.
ISVLSI 2007: 239-244 |
| 155 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu:
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.
ISVLSI 2007: 383-388 |
| 154 | EE | Yaoguang Wei,
Sheqin Dong,
Xianlong Hong,
Yuchun Ma:
An accurate and efficient probabilistic congestion estimation model in x architecture.
SLIP 2007: 25-32 |
| 153 | EE | Zhuoyuan Li,
Xianlong Hong,
Qiang Zhou,
Shan Zeng,
Jinian Bian,
Wenjian Yu,
Hannah Honghua Yang,
Vijay Pitchumani,
Chung-Kuan Cheng:
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 645-658 (2007) |
| 152 | EE | Jin Shi,
Yici Cai,
Sheldon X.-D. Tan,
Jeffrey Fan,
Xianlong Hong:
Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 680-692 (2007) |
| 151 | EE | Yici Cai,
Bin Liu,
Qiang Zhou,
Xianlong Hong:
Voltage Island Generation in Cell Based Dual-Vdd Design.
IEICE Transactions 90-A(1): 267-273 (2007) |
| 150 | EE | Yibo Wang,
Yici Cai,
Xianlong Hong,
Yi Zou:
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration.
IEICE Transactions 90-A(5): 1028-1037 (2007) |
| 149 | EE | Yongqiang Lu,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Jun Gu:
An efficient quadratic placement based on search space traversing technology.
Integration 40(3): 253-260 (2007) |
| 148 | EE | Yaoguang Wei,
Sheqin Dong,
Xianlong Hong:
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement.
Integration 40(4): 406-419 (2007) |
| 147 | EE | Jeffrey Fan,
Sheldon X.-D. Tan,
Yici Cai,
Xianlong Hong:
Partitioning-based decoupling capacitor budgeting via sequence of linear programming.
Integration 40(4): 516-524 (2007) |
| 146 | EE | Qiang Zhou,
Yici Cai,
Duo Li,
Xianlong Hong:
A Yield-Driven Gridless Router.
J. Comput. Sci. Technol. 22(5): 653-660 (2007) |
| 2006 |
|---|
| 145 | EE | Xianlong Hong,
Yici Cai,
Hailong Yao,
Duo Li:
DFM-aware Routing for Yield Enhancement.
APCCAS 2006: 1091-1094 |
| 144 | EE | Qiang Zhou,
Yi Zou,
Yici Cai,
Xianlong Hong:
Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials.
APCCAS 2006: 1635-1638 |
| 143 | EE | Liu Yang,
Sheqin Dong,
Xianlong Hong,
Yuchun Ma:
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints.
APCCAS 2006: 792-795 |
| 142 | EE | Bin Liu,
Yici Cai,
Qiang Zhou,
Xianlong Hong:
Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.
ASP-DAC 2006: 582-587 |
| 141 | EE | Zhen Cao,
Tong Jing,
Yu Hu,
Yiyu Shi,
Xianlong Hong,
Xiaodong Hu,
Guiying Yan:
DraXRouter: global routing in X-Architecture with dynamic resource assignment.
ASP-DAC 2006: 618-623 |
| 140 | EE | Yiyu Shi,
Tong Jing,
Lei He,
Zhe Feng,
Xianlong Hong:
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model.
ASP-DAC 2006: 630-635 |
| 139 | EE | Di Long,
Xianlong Hong,
Sheqin Dong:
Signal-path driven partition and placement for analog circuit.
ASP-DAC 2006: 694-699 |
| 138 | EE | Jin Shi,
Yici Cai,
Sheldon X.-D. Tan,
Xianlong Hong:
Efficient early stage resonance estimation techniques for C4 package.
ASP-DAC 2006: 826-831 |
| 137 | EE | Xin Zhao,
Yici Cai,
Qiang Zhou,
Xianlong Hong:
A novel low-power physical design methodology for MTCMOS.
ISCAS 2006 |
| 136 | EE | Lijuan Luo,
Qiang Zhou,
Yici Cai,
Xianlong Hong,
Yibo Wang:
A novel technique integrating buffer insertion into timing driven placement.
ISCAS 2006 |
| 135 | EE | Hongjie Bai,
Sheqin Dong,
Xianlong Hong,
Song Chen:
Buffer planning based on block exchanging.
ISCAS 2006 |
| 134 | EE | Hailong Yao,
Yici Cai,
Xianlong Hong:
Congestion-driven W-shape multilevel full-chip routing framework.
ISCAS 2006 |
| 133 | EE | Sheqin Dong,
Shuyi Zheng,
Xianlong Hong:
Floorplanning for 2.5-D system integration using multi-layer-BSG structure.
ISCAS 2006 |
| 132 | EE | Weixiang Shen,
Yici Cai,
Jiang Hu,
Xianlong Hong,
Bing Lu:
High performance clock routing in X-architecture.
ISCAS 2006 |
| 131 | EE | Shaojun Wei,
Sheqin Dong,
Xianlong Hong,
Youliang Wu:
On handling the fixed-outline constraints of floorplanning using less flexibility first principles.
ISCAS 2006 |
| 130 | EE | Yibo Wang,
Yici Cai,
Xianlong Hong:
Performance and power aware buffered tree construction.
ISCAS 2006 |
| 129 | EE | Jin Shi,
Yici Cai,
Sheldon X.-D. Tan,
Xianlong Hong:
High accurate pattern based precondition method for extremely large power/ground grid analysis.
ISPD 2006: 108-113 |
| 128 | EE | Zhuoyuan Li,
Xianlong Hong,
Qiang Zhou,
Shan Zeng,
Jinian Bian,
Hannah Honghua Yang,
Vijay Pitchumani,
Chung-Kuan Cheng:
Integrating dynamic thermal via planning with 3D floorplanning algorithm.
ISPD 2006: 178-185 |
| 127 | EE | Zhe Feng,
Yu Hu,
Tong Jing,
Xianlong Hong,
Xiaodong Hu,
Guiying Yan:
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane.
ISPD 2006: 48-55 |
| 126 | EE | Xinjie Wei,
Yici Cai,
Xianlong Hong:
Clock Skew Scheduling Under Process Variations.
ISQED 2006: 237-242 |
| 125 | EE | Jeffrey Fan,
I-Fan Liao,
Sheldon X.-D. Tan,
Yici Cai,
Xianlong Hong:
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming.
ISQED 2006: 272-277 |
| 124 | EE | Sheqin Dong,
Fan Guo,
Jun Yuan,
Rensheng Wang,
Xianlong Hong:
A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle.
JCIS 2006 |
| 123 | EE | Sheqin Dong,
Rensheng Wang,
Fan Guo,
Jun Yuan,
Xianlong Hong:
Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree.
JCIS 2006 |
| 122 | EE | Sheqin Dong,
Fan Guo,
Jun Yuan,
Rensheng Wang,
Xianlong Hong:
Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study.
JCIS 2006 |
| 121 | EE | Zhuoyuan Li,
Xianlong Hong,
Qiang Zhou,
Jinian Bian,
Hannah Honghua Yang,
Vijay Pitchumani:
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration.
ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006) |
| 120 | EE | Hang Li,
Jeffrey Fan,
Zhenyu Qi,
Sheldon X.-D. Tan,
Lifeng Wu,
Yici Cai,
Xianlong Hong:
Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2402-2412 (2006) |
| 119 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing,
Ling Zhang,
Jun Gu:
A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design.
Integration 39(4): 457-473 (2006) |
| 118 | EE | Yu Hu,
Tong Jing,
Zhe Feng,
Xianlong Hong,
Xiaodong Hu,
Guiying Yan:
ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm.
J. Comput. Sci. Technol. 21(1): 147-152 (2006) |
| 117 | EE | Yici Cai,
Bin Liu,
Yan Xiong,
Qiang Zhou,
Xianlong Hong:
Priority-Based Routing Resource Assignment Considering Crosstalk.
J. Comput. Sci. Technol. 21(6): 913-921 (2006) |
| 116 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Chung-Kuan Cheng,
Jun Gu:
General Floorplans with L/T-Shaped Blocks Using Corner Block List.
J. Comput. Sci. Technol. 21(6): 922-926 (2006) |
| 115 | EE | Zuying Luo,
Yici Cai,
Sheldon X.-D. Tan,
Xianlong Hong,
Xiaoyi Wang,
Zhu Pan,
Jingjing Fu:
Time-domain analysis methodology for large-scale RLC circuits and its applications.
Science in China Series F: Information Sciences 49(5): 665-680 (2006) |
| 114 | EE | Xinjie Wei,
Yici Cai,
Meng Zhao,
Xianlong Hong:
Legitimate Skew Clock Routing with Buffer Insertion.
VLSI Signal Processing 42(2): 107-116 (2006) |
| 2005 |
|---|
| 113 | EE | Hailong Yao,
Yici Cai,
Xianlong Hong,
Qiang Zhou:
Improved multilevel routing with redundant via placement for yield and reliability.
ACM Great Lakes Symposium on VLSI 2005: 143-146 |
| 112 | EE | Rong Liu,
Sheqin Dong,
Xianlong Hong:
Fixed-outline floorplanning based on common subsequence.
ACM Great Lakes Symposium on VLSI 2005: 156-159 |
| 111 | EE | Qinglang Luo,
Xianlong Hong,
Qiang Zhou,
Yici Cai:
A new algorithm for layout of dark field alternating phase shifting masks.
ACM Great Lakes Symposium on VLSI 2005: 221-224 |
| 110 | EE | Xiren Wang,
Wenjian Yu,
Zeyi Wang,
Xianlong Hong:
An improved direct boundary element method for substrate coupling resistance extraction.
ACM Great Lakes Symposium on VLSI 2005: 84-87 |
| 109 | EE | Yang Yang,
Tong Jing,
Xianlong Hong,
Yu Hu,
Qi Zhu,
Xiaodong Hu,
Guiying Yan:
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield.
ASAP 2005: 198-203 |
| 108 | EE | Yin Wang,
Xianlong Hong,
Tong Jing,
Yang Yang,
Xiaodong Hu,
Guiying Yan:
The polygonal contraction heuristic for rectilinear Steiner tree construction.
ASP-DAC 2005: 1-6 |
| 107 | EE | Yici Cai,
Zhu Pan,
Sheldon X.-D. Tan,
Xianlong Hong,
Wenting Hou,
Lifeng Wu:
Relaxed hierarchical power/ground grid analysis.
ASP-DAC 2005: 1090-1093 |
| 106 | EE | Renshen Wang,
Sheqin Dong,
Xianlong Hong:
An improved P-admissible floorplan representation based on Corner Block List.
ASP-DAC 2005: 1115-1118 |
| 105 | EE | Jun Yuan,
Sheqin Dong,
Xianlong Hong,
Yuliang Wu:
LFF algorithm for heterogeneous FPGA floorplanning.
ASP-DAC 2005: 1123-1126 |
| 104 | EE | Tong Jing,
Ling Zhang,
Jinghong Liang,
Jingyu Xu,
Xianlong Hong,
Jinjun Xiong,
Lei He:
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.
ASP-DAC 2005: 115-120 |
| 103 | EE | Yongqiang Lu,
Cliff C. N. Sze,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Liang Huang,
Jiang Hu:
Register placement for low power clock network.
ASP-DAC 2005: 588-593 |
| 102 | EE | Yu Hu,
Tong Jing,
Xianlong Hong,
Zhe Feng,
Xiaodong Hu,
Guiying Yan:
An-OARSMan: obstacle-avoiding routing tree construction with good length performance.
ASP-DAC 2005: 7-12 |
| 101 | EE | Jingjing Fu,
Zuying Luo,
Xianlong Hong,
Yici Cai,
Sheldon X.-D. Tan,
Zhu Pan:
VLSI on-chip power/ground network optimization considering decap leakage currents.
ASP-DAC 2005: 735-738 |
| 100 | EE | Yi Zou,
Qiang Zhou,
Yici Cai,
Xianlong Hong,
Sheldon X.-D. Tan:
Analysis of buffered hybrid structured clock networks.
ASP-DAC 2005: 93-98 |
| 99 | EE | Liang Huang,
Yici Cai,
Qiang Zhou,
Xianlong Hong,
Jiang Hu,
Yongqiang Lu:
Clock network minimization methodology based on incremental placement.
ASP-DAC 2005: 99-102 |
| 98 | EE | Hang Li,
Zhenyu Qi,
Sheldon X.-D. Tan,
Lifeng Wu,
Yici Cai,
Xianlong Hong:
Partitioning-based approach to fast on-chip decap budgeting and minimization.
DAC 2005: 170-175 |
| 97 | EE | Yongqiang Lu,
Cliff C. N. Sze,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Liang Huang,
Jiang Hu:
Navigating registers in placement for clock network minimization.
DAC 2005: 176-181 |
| 96 | EE | Hongjie Bai,
Sheqin Dong,
Xianlong Hong,
Song Chen:
A New Buffer Planning Algorithm Based on Room Resizing.
EUC 2005: 291-299 |
| 95 | EE | Lijuan Luo,
Qiang Zhou,
Xianlong Hong,
Hanbin Zhou:
Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design.
ICCSA (4) 2005: 896-905 |
| 94 | EE | Yunfeng Wang,
Jinian Bian,
Xianlong Hong,
Liu Yang,
Qiang Zhou,
Qiang Wu:
A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design.
ICESS 2005: 275-286 |
| 93 | EE | Yici Cai,
Bin Liu,
Xiong Yan,
Qiang Zhou,
Xianlong Hong:
A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem.
ICNC (3) 2005: 181-184 |
| 92 | EE | Xinjie Wei,
Yici Cai,
Xianlong Hong:
Zero skew clock routing with tree topology construction using simulated annealing method.
ISCAS (1) 2005: 101-104 |
| 91 | EE | Yici Cai,
Yibo Wang,
Xianlong Hong:
A global interconnect optimization algorithm under accurate delay model using solution space smoothing.
ISCAS (1) 2005: 93-96 |
| 90 | EE | Yiqian Zhang,
Xianlong Hong,
Yici Cai:
An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models.
ISCAS (1) 2005: 97-100 |
| 89 | EE | Zhe Zhou,
Sheqin Dong,
Xianlong Hong,
Yuliang Wu,
Yoji Kajitani:
A new approach based on LFF for optimization of dynamic hardware reconfigurations.
ISCAS (2) 2005: 1210-1213 |
| 88 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Song Chen,
Chung-Kuan Cheng:
Performance constrained floorplanning based on partial clustering [IC layout].
ISCAS (2) 2005: 1863-1866 |
| 87 | EE | Yici Cai,
Bin Liu,
Qiang Zhou,
Xianlong Hong:
Integrated routing resource assignment for RLC crosstalk minimization.
ISCAS (2) 2005: 1871-1874 |
| 86 | EE | Rong Liu,
Sheqin Dong,
Xianlong Hong,
Yoji Kajitani:
Fixed-outline floorplanning with constraints through instance augmentation.
ISCAS (2) 2005: 1883-1886 |
| 85 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing:
Timing-driven global routing with efficient buffer insertion.
ISCAS (3) 2005: 2449-2452 |
| 84 | EE | Di Long,
Xianlong Hong,
Sheqin Dong:
Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit.
ISCAS (3) 2005: 2999-3002 |
| 83 | EE | Yunfeng Wang,
Jinian Bian,
Xianlong Hong:
Interconnect delay optimization via high level re-synthesis after floorplanning.
ISCAS (6) 2005: 5641-5644 |
| 82 | EE | Song Chen,
Xianlong Hong,
Sheqin Dong,
Yuchun Ma,
Chung-Kuan Cheng:
VLSI block placement with alignment constraints based on corner block list.
ISCAS (6) 2005: 6222-6225 |
| 81 | EE | Zhuoyuan Li,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Jinian Bian,
Hannal Yang,
Prashant Saxena,
Vijay Pitchumani:
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.
ISCAS (6) 2005: 6230-6233 |
| 80 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Song Chen,
Chung-Kuan Cheng:
Buffer Planning Algorithm Based on Partial Clustered Floorplanning.
ISQED 2005: 213-219 |
| 79 | EE | Zhenyu Qi,
Hang Li,
Sheldon X.-D. Tan,
Lifeng Wu,
Yici Cai,
Xianlong Hong:
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery.
ISQED 2005: 542-547 |
| 78 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing,
Yang Yang:
Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design.
ISQED 2005: 616-621 |
| 77 | EE | Song Chen,
Xianlong Hong,
Sheqin Dong,
Yuchun Ma,
Chung-Kuan Cheng:
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.
ISQED 2005: 628-633 |
| 76 | EE | Yici Cai,
Bin Liu,
Qiang Zhou,
Xianlong Hong:
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design.
PATMOS 2005: 257-266 |
| 75 | EE | Jin Shi,
Yici Cai,
Xianlong Hong,
Sheldon X.-D. Tan:
Efficient Simulation of Power/Ground Networks with Package and Vias.
PATMOS 2005: 318-328 |
| 74 | EE | Yu Hu,
Tong Jing,
Xianlong Hong,
Xiaodong Hu,
Guiying Yan:
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design.
SAMOS 2005: 344-353 |
| 73 | EE | Yibo Wang,
Yici Cai,
Xianlong Hong:
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.
VLSI Design 2005: 91-96 |
| 72 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Song Chen,
Chung-Kuan Cheng,
Jun Gu:
Buffer planning as an Integral part of floorplanning with consideration of routing congestion.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 609-621 (2005) |
| 71 | EE | Qi Zhu,
Hai Zhou,
Tong Jing,
Xianlong Hong,
Yang Yang:
Spanning graph-based nonrectilinear steiner tree algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1066-1075 (2005) |
| 70 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing:
Timing-Driven Global Routing with Efficient Buffer Insertion.
IEICE Transactions 88-A(11): 3188-3195 (2005) |
| 69 | EE | Yongqiang Lu,
Chin-Ngai Sze,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Liang Huang,
Jiang Hu:
Navigating Register Placement for Low Power Clock Network Design.
IEICE Transactions 88-A(12): 3405-3411 (2005) |
| 68 | EE | Bin Liu,
Yici Cai,
Qiang Zhou,
Xianlong Hong:
Crosstalk and Congestion Driven Layer Assignment Algorithm.
IEICE Transactions 88-A(6): 1565-1572 (2005) |
| 67 | EE | Yi Zou,
Yici Cai,
Qiang Zhou,
Xianlong Hong,
Sheldon X.-D. Tan:
A Fast Delay Computation for the Hybrid Structured Clock Network.
IEICE Transactions 88-A(7): 1964-1970 (2005) |
| 66 | EE | Yici Cai,
Jin Shi,
Zuying Luo,
Xianlong Hong:
Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain.
J. Comput. Sci. Technol. 20(2): 224-230 (2005) |
| 65 | EE | Hailong Yao,
Yici Cai,
Qiang Zhou,
Xianlong Hong:
Crosstalk-Aware Routing Resource Assignment.
J. Comput. Sci. Technol. 20(2): 231-236 (2005) |
| 64 | EE | Yici Cai,
Xin Zhao,
Qiang Zhou,
Xianlong Hong:
Shielding Area Optimization Under the Solution of Interconnect Crosstalk.
J. Comput. Sci. Technol. 20(6): 901-906 (2005) |
| 2004 |
|---|
| 63 | EE | Jingjing Fu,
Zuying Luo,
Xianlong Hong,
Yici Cai,
Sheldon X.-D. Tan,
Zhu Pan:
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery.
ASP-DAC 2004: 505-510 |
| 62 | EE | Song Chen,
Xianlong Hong,
Sheqin Dong,
Yuchun Ma,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu:
A buffer planning algorithm with congestion optimization.
ASP-DAC 2004: 615-620 |
| 61 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Song Chen,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu:
Buffer allocation algorithm with consideration of routing congestion.
ASP-DAC 2004: 621-623 |
| 60 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing,
Ling Zhang,
Jun Gu:
A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design.
ASP-DAC 2004: 677-682 |
| 59 | EE | Qi Zhu,
Hai Zhou,
Tong Jing,
Xianlong Hong,
Yang Yang:
Efficient octilinear Steiner tree construction based on spanning graphs.
ASP-DAC 2004: 687-690 |
| 58 | EE | Yi Zou,
Yici Cai,
Qiang Zhou,
Xianlong Hong,
Sheldon X.-D. Tan:
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.
ICCD 2004: 344-349 |
| 57 | | Weikun Guo,
Sheldon X.-D. Tan,
Zuying Luo,
Xianlong Hong:
Partial random walk for large linear network analysis.
ISCAS (5) 2004: 173-177 |
| 56 | | Yang Wang,
Yici Cai,
Xianlong Hong,
Qiang Zhou:
Algorithm for yield driven correction of layout.
ISCAS (5) 2004: 241-245 |
| 55 | | Xin Zhao,
Yici Cai,
Qiang Zhou,
Xianlong Hong,
Lei He,
Jinjun Xiong:
Shielding area optimization under the solution of interconnect crosstalk.
ISCAS (5) 2004: 297-300 |
| 54 | | Meng Zhao,
Xinjie Wei,
Yici Cai,
Xianlong Hong:
Quick and effective buffered legitimate skew clock routing.
ISCAS (5) 2004: 337-340 |
| 53 | | Sheqin Dong,
Zhong Yang,
Xianlong Hong,
Yuliang Wu:
Module placement based on quadratic programming and rectangle packing using less flexibility first principle.
ISCAS (5) 2004: 61-64 |
| 52 | | Ling Zhang,
Tong Jing,
Xianlong Hong,
Jingyu Xu,
Jinjun Xiong,
Lei He:
Performance and RLC crosstalk driven global routing.
ISCAS (5) 2004: 65-68 |
| 51 | | Changqi Yang,
Xianlong Hong,
Hannah Honghua Yang,
Qiang Zhou,
Yici Cai,
Yongqiang Lu:
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.
ISCAS (5) 2004: 81-84 |
| 50 | | Bin Liu,
Yici Cai,
Qiang Zhou,
Xianlong Hong:
Layer assignment algorithm for RLC crosstalk minimization.
ISCAS (5) 2004: 85-88 |
| 49 | | Hailong Yao,
Qiang Zhou,
Xianlong Hong,
Yici Cai:
Crosstalk driven routing resource assignment.
ISCAS (5) 2004: 89-92 |
| 48 | EE | Zhu Pan,
Yici Cai,
Sheldon X.-D. Tan,
Zuying Luo,
Xianlong Hong:
Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling.
ISQED 2004: 63-68 |
| 47 | EE | Jingjing Fu,
Zuying Luo,
Xianlong Hong,
Yici Cai,
Sheldon X.-D. Tan,
Zhu Pan:
Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.
PATMOS 2004: 433-441 |
| 46 | EE | Yin Wang,
Xianlong Hong,
Tong Jing,
Yang Yang,
Xiaodong Hu,
Guiying Yan:
An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design.
PATMOS 2004: 442-452 |
| 45 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu:
Stairway compaction using corner block list and its applications with rectilinear blocks.
ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004) |
| 44 | EE | Tong Jing,
Xianlong Hong,
Jingyu Xu,
Haiyun Bao,
Chung-Kuan Cheng,
Jun Gu:
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 358-365 (2004) |
| 43 | EE | Xiaohai Wu,
Xianlong Hong,
Yici Cai,
Zuying Luo,
Chung-Kuan Cheng,
Jun Gu,
Wayne Wei-Ming Dai:
Area minimization of power distribution network using efficient nonlinear programming techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1086-1094 (2004) |
| 42 | EE | Yongjun Xu,
Zuying Luo,
Xiaowei Li,
Li-Jian Li,
Xianlong Hong:
Leakage Current Estimation of CMOS Circuit with Stack Effect.
J. Comput. Sci. Technol. 19(5): 708-717 (2004) |
| 41 | EE | Song Chen,
Xianlong Hong,
Sheqin Dong,
Yuchun Ma,
Chung-Kuan Cheng,
Jun Gu:
Fast Evaluation of Bounded Slice-Line Grid.
J. Comput. Sci. Technol. 19(6): 973-980 (2004) |
| 2003 |
|---|
| 40 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Song Chen,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu:
Dynamic global buffer planning optimization based on detail block locating and congestion analysis.
DAC 2003: 806-811 |
| 39 | EE | Wenjian Yu,
Zeyi Wang,
Xianlong Hong:
Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics.
ICCD 2003: 58-63 |
| 38 | EE | Song Chen,
Xianlong Hong,
Sheqin Dong,
Yuchun Ma,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu:
Evaluating a bounded slice-line grid assignment in O(nlogn) time.
ISCAS (4) 2003: 708-711 |
| 37 | EE | Rui Liu,
Sheqin Dong,
Xianlong Hong,
Di Long,
Jun Gu:
Algorithms for analog VLSI 2D stack generation and block merging.
ISCAS (4) 2003: 716-719 |
| 36 | EE | Yongqiang Lu,
Xianlong Hong,
Wenting Hou,
Weimin Wu,
Yici Cai:
Combining clustering and partitioning in quadratic placement.
ISCAS (4) 2003: 720-723 |
| 35 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Yici Cai,
Song Chen,
Chung-Kuan Cheng,
Jun Gu:
Arbitrary convex and concave rectilinear block packing based on corner block list.
ISCAS (5) 2003: 493-496 |
| 34 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Song Chen,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu:
An integrated floorplanning with an efficient buffer planning algorithm.
ISPD 2003: 136-142 |
| 33 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing,
Yici Cai,
Jun Gu:
An efficient hierarchical timing-driven Steiner tree algorithm for global routing.
Integration 35(2): 69-84 (2003) |
| 32 | EE | Wenting Hou,
Xianlong Hong,
Weimin Wu,
Yici Cai:
FaSa: A Fast and Stable Quadratic Placement Algorithm.
J. Comput. Sci. Technol. 18(3): 318-324 (2003) |
| 31 | EE | Tong Jing,
Xianlong Hong,
Haiyun Bao,
Jingyu Xu,
Gu Jun:
SSTT: Efficient Local Search for GSI Global Routing.
J. Comput. Sci. Technol. 18(5): 632-640 (2003) |
| 30 | EE | Xianlong Hong,
Tong Jing,
Jingyu Xu,
Haiyun Bao,
Gu Jun:
CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing.
J. Comput. Sci. Technol. 18(6): 732-738 (2003) |
| 29 | EE | Sheqin Dong,
Xianlong Hong,
Yuliang Wu,
Jun Gu:
Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle.
J. Comput. Sci. Technol. 18(6): 739-746 (2003) |
| 2002 |
|---|
| 28 | EE | Shuzhou Fang,
Zeyi Wang,
Xianlong Hong:
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI.
ASP-DAC 2002: 305-310 |
| 27 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu:
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks.
ASP-DAC 2002: 387-392 |
| 26 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing,
Yici Cai,
Jun Gu:
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing.
ASP-DAC 2002: 473-478 |
| 25 | EE | Tong Jing,
Xianlong Hong,
Haiyun Bao,
Yici Cai,
Jingyu Xu,
Jun Gu:
A novel and efficient timing-driven global router for standard cell layout design based on critical network concept.
ISCAS (1) 2002: 165-168 |
| 24 | EE | Shuzhou Fang,
Zeyi Wang,
Xianlong Hong:
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI.
VLSI Design 2002: 305-310 |
| 23 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu:
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks.
VLSI Design 2002: 387-392 |
| 22 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing,
Yici Cai,
Jun Gu:
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing.
VLSI Design 2002: 473-478 |
| 21 | EE | Sheqin Dong,
Shuo Zhou,
Xianlong Hong,
Chung-Kuan Cheng,
Jun Gu,
Yici Cai:
An Optimum Placement Search Algorithm Based on Extended Corner Block List.
J. Comput. Sci. Technol. 17(6): 699-707 (2002) |
| 2001 |
|---|
| 20 | EE | Yuchun Ma,
Sheqin Dong,
Xianlong Hong,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu:
VLSI floorplanning with boundary constraints based on corner block list.
ASP-DAC 2001: 509-514 |
| 19 | EE | Sheqin Dong,
Xianlong Hong,
Youliang Wu,
Yizhou Lin,
Jun Gu:
VLSI block placement using less flexibility first principles.
ASP-DAC 2001: 601-604 |
| 18 | EE | Wenting Hou,
Hong Yu,
Xianlong Hong,
Yici Cai,
Weimin Wu,
Jun Gu,
William H. Kao:
A new congestion-driven placement algorithm based on cell inflation.
ASP-DAC 2001: 605-608 |
| 17 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu:
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.
DAC 2001: 770-775 |
| 16 | EE | Xiaohai Wu,
Xianlong Hong,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu,
Wayne Wei-Ming Dai:
Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques.
ICCAD 2001: 153-157 |
| 15 | EE | Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Yici Cai,
Chung-Kuan Cheng,
Jun Gu:
Floorplanning with abutment constraints based on corner block list.
Integration 31(1): 65-77 (2001) |
| 2000 |
|---|
| 14 | EE | Zhang Yan,
Wang Baohua,
Yici Cai,
Xianlong Hong:
Area routing oriented hierarchical corner stitching with partial bin.
ASP-DAC 2000: 105-110 |
| 13 | EE | Hong Yu,
Xianlong Hong,
Yici Cai:
MMP: a novel placement algorithm for combined macro block and standard cell layout design.
ASP-DAC 2000: 271-276 |
| 12 | EE | Jiangchun Gu,
Zeyi Wang,
Xianlong Hong:
Hierarchical computation of 3-D interconnect capacitance using direct boundary element method.
ASP-DAC 2000: 447-452 |
| 11 | EE | Shuzhou Fang,
Xiaobo Tang,
Zeyi Wang,
Xianlong Hong:
A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section.
ASP-DAC 2000: 453-456 |
| 10 | | Xianlong Hong,
Gang Huang,
Yici Cai,
Jiangchun Gu,
Sheqin Dong,
Chung-Kuan Cheng,
Jun Gu:
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan.
ICCAD 2000: 8-12 |
| 1999 |
|---|
| 9 | EE | Xiaohai Wu,
Changge Qiao,
Xianlong Hong:
Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells.
ASP-DAC 1999: 21- |
| 8 | EE | Haiyun Bao,
Xianlong Hong,
Yici Cai:
A New Global Routing Algorithm Independent Of Net Ordering.
ASP-DAC 1999: 245-248 |
| 7 | EE | Gang Huang,
Xianlong Hong,
Changge Qiao,
Yici Cai:
A Timing-Driven Block Placer Based on Sequence Pair Model.
ASP-DAC 1999: 249-252 |
| 6 | EE | Jinsong Bei,
Hongxing Li,
Jinian Bian,
Hongxi Xue,
Xianlong Hong:
FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking.
ASP-DAC 1999: 363- |
| 5 | EE | Jinsong Hou,
Zeyi Wang,
Xianlong Hong:
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance.
ASP-DAC 1999: 93- |
| 1997 |
|---|
| 4 | EE | Xianlong Hong,
Tianxiong Xue,
Jin Huang,
Chung-Kuan Cheng,
Ernest S. Kuh:
TIGER: an efficient timing-driven global router for gate array and standard cell layout design.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1323-1331 (1997) |
| 1993 |
|---|
| 3 | EE | Xianlong Hong,
Tianxiong Xue,
Ernest S. Kuh,
Chung-Kuan Cheng,
Jin Huang:
Performance-Driven Steiner Tree Algorithm for Global Routing.
DAC 1993: 177-181 |
| 2 | EE | Jin Huang,
Xianlong Hong,
Chung-Kuan Cheng,
Ernest S. Kuh:
An Efficient Timing-Driven Global Routing Algorithm.
DAC 1993: 596-600 |
| 1992 |
|---|
| 1 | EE | Xianlong Hong,
Jin Huang,
Chung-Kuan Cheng,
Ernest S. Kuh:
FARM: An Efficient Feed-Through Pin Assignment Algorithm.
DAC 1992: 530-535 |
