 | 2009 |
|---|
| 15 |       | Liang-Bi Chen,
Ruei-Ting Gu,
Wei-Sheng Huang,
Chien-Chou Wang,
Wen-Chi Shiue,
Tsung-Yu Ho,
Yun-Nan Chang,
Shen-Fu Hsiao,
Chung-Nan Lee,
Ing-Jer Huang:
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics.
ASP-DAC 2009: 131-132 |
| 2008 |
|---|
| 14 | | Shen-Fu Hsiao,
Ming-Yu Tsai,
Chia-Sheng Wen:
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction.
ISCAS 2008: 2022-2025 |
| 13 | | Shen-Fu Hsiao,
Ping-Chung Wei,
Ching-Pin Lin:
An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches.
ISCAS 2008: 468-471 |
| 2006 |
|---|
| 12 | | Shen-Fu Hsiao,
Sze-Yun Lin,
Tze-Chong Cheng,
Ming-Yu Tsai:
An Automatic Cache Generator Based on Content-Addressable Memory.
APCCAS 2006: 1313-1316 |
| 11 | | Shen-Fu Hsiao,
Ming-Yu Tsai,
Chia-Sheng Wen:
Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits.
APCCAS 2006: 1631-1634 |
| 10 | | Shen-Fu Hsiao,
Yo-Chi Chen,
Ming-Yu Tsai,
Tze-Chong Cheng:
Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding.
MTDT 2006: 34-42 |
| 2005 |
|---|
| 9 | | Shen-Fu Hsiao,
Ming-Yu Tsai,
Ming-Chih Chen,
Chia-Sheng Wen:
An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.
ISCAS (3) 2005: 2433-2436 |
| 8 | | Tso-Bing Juang,
Shen-Fu Hsiao,
Ming-Yu Tsai,
Jenq-Shiun Jan:
A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition.
IEICE Transactions 88-D(7): 1464-1471 (2005) |
| 2002 |
|---|
| 7 | | Tso-Bing Juang,
Jeng-Hsiun Jan,
Ming-Yu Tsai,
Shen-Fu Hsiao:
Partition methodology for the final adder in a tree-structure parallel multiplier generator.
APCCAS (1) 2002: 471-474 |
| 2001 |
|---|
| 6 |  | Shen-Fu Hsiao,
Wei-Ren Shiue:
A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array.
IEEE Trans. Circuits Syst. Video Techn. 11(11): 1149-1159 (2001) |
| 5 | | Shen-Fu Hsiao,
Jian-Ming Tseng:
Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec.
VLSI Signal Processing 28(3): 205-220 (2001) |
| 2000 |
|---|
| 4 | | Shen-Fu Hsiao,
Chun-Yi Lau,
Jean-Marc Delosme:
Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD.
VLSI Signal Processing 25(2): 155-166 (2000) |
| 1999 |
|---|
| 3 | | Shen-Fu Hsiao:
A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations.
ISCAS (1) 1999: 455-458 |
| 1998 |
|---|
| 2 | | Shen-Fu Hsiao,
Jen-Yin Chen:
Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure.
VLSI Signal Processing 20(3): 267-278 (1998) |
| 1995 |
|---|
| 1 | | Shen-Fu Hsiao,
Jean-Marc Delosme:
Householder CORDIC Algorithms.
IEEE Trans. Computers 44(8): 990-1001 (1995) |
