Chenming Hu

	2005
22		Jin He, Jane Xi, Mansun Chan, Hui Wan, Mohan V. Dunga, Babak Heydari, Ali M. Niknejad, Chenming Hu: Charge-Based Core and the Model Architecture of BSIM5. ISQED 2005: 96-101
21		Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu: Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. IEEE Trans. VLSI Syst. 13(1): 158-162 (2005)
	2004
20		Jin He, Xuemei Xi, Mansun Chan, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu: A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach. ISQED 2004: 45-50
	2003
19		Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: Improved a priori interconnect predictions and technology extrapolation in the GTX system. IEEE Trans. VLSI Syst. 11(1): 3-14 (2003)
18		Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu: Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 560-572 (2003)
17		Mansun Chan, Xuemei Xi, Jin He, Kanyu M. Cao, Mohan V. Dunga, Ali M. Niknejad, Ping K. Ko, Chenming Hu: Practical compact modeling approaches and options for sub-0.1 mum CMOS technologies. Microelectronics Reliability 43(3): 399-404 (2003)
	2002
16		Pin Su, Samel K. H. Fung, Weidong Liu, Chenming Hu: Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD. ISQED 2002: 487-491
15		Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu: Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. VLSI Design 2002: 77-
14		Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu: Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. IEEE Trans. VLSI Syst. 10(6): 799-805 (2002)
13		Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 544-553 (2002)
	2001
12		Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie: Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. ISQED 2001: 185-190
	2000
11		Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester: Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. ICCAD 2000: 56-61
10		Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD 2000: 62-67
	1999
9		Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu: On Thermal Effects in Deep Sub-Micron VLSI Interconnects. DAC 1999: 885-891
	1998
8		Michael Orshansky, James C. Chen, Chenming Hu: A Statistical Performance Simulation Methodology for VLSI Circuits. DAC 1998: 402-407
7		Yuhua Cheng, Kai Chen, Kiyotaka Imai, Chenming Hu: A unified MOSFET channel charge model for device modeling in circuit simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 641-644 (1998)
	1997
6		Kai Chen, Chenming Hu: Device and technology optimizations for low power design in deep sub-micron regime. ISLPED 1997: 312-316
	1996
5		Kai Chen, Yuhua Cheng, Chenming Hu: Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models. ISLPED 1996: 197-200
	1993
4		Robert H. Tu, Elyse Rosenbaum, Wilson Y. Chan, Chester C. Li, Eric Minami, Khandker Quader, Ping K. Ko, Chenming Hu: Berkeley reliability tools-BERT. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1524-1534 (1993)
	1992
3		Hong June Park, Ping Keung Ko, Chenming Hu: A non-quasi-static MOSFET model for SPICE-AC analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1247-1257 (1992)
	1991
2		Hong June Park, Ping Keung Ko, Chenming Hu: A charge sheet capacitance model of short channel MOSFETs for SPICE. IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 376-389 (1991)
1		Hong June Park, Ping Keung Ko, Chenming Hu: A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 629-642 (1991)

Coauthor Index

1	Kanak Agarwal	[15] [18]
2	Kaustav Banerjee	[9]
3	Kanyu M. Cao	[17]
4	Yu Cao	[11] [12] [14] [15] [18] [19] [21]
5	Mansun Chan	[17] [20] [22]
6	Wilson Y. Chan	[4]
7	N. H. Chang	[14]
8	Norman Chang	[12]
9	James C. Chen	[8]
10	Pinhong Chen	[10] [13]
11	Kai Chen	[5] [6] [7]
12	Yuhua Cheng	[5] [7]
13	Mohan V. Dunga	[17] [22]
14	Samel K. H. Fung	[16]
15	Jin He	[17] [20] [22]
16	Babak Heydari	[22]
17	Xuejue Huang	[11] [12] [14] [19] [21]
18	Kiyotaka Imai	[7]
19	Andrew B. Kahng	[11] [19]
20	Kurt Keutzer	[10] [13]
21	Tsu-Jae King	[21]
22	Ping K. Ko	[4] [17]
23	Ping Keung Ko	[1] [2] [3]
24	Chester C. Li	[4]
25	Chung-Hsun Lin	[20]
26	Shen Lin	[12] [14]
27	Weidong Liu	[16]
28	Igor L. Markov	[19]
29	Amit Mehrotra	[9]
30	Linda S. Milor (Linda Milor)	[10] [13]
31	Eric Minami	[4]
32	Sudhakar Muddu	[11]
33	O. Sam Nakagawa	[12] [14]
34	Ali M. Niknejad	[17] [20] [22]
35	Michael Oliver	[19]
36	Michael Orshansky	[8] [10] [13]
37	Hong June Park	[1] [2] [3]
38	Khandker Quader	[4]
39	Elyse Rosenbaum	[4]
40	Alberto L. Sangiovanni-Vincentelli	[9]
41	Takashi Sato	[15] [18]
42	Dirk Stroobandt	[11] [19]
43	Pin Su	[16]
44	Dennis Sylvester	[11] [14] [15] [18] [19] [21]
45	Robert H. Tu	[4]
46	Hui Wan	[22]
47	Jane Xi	[22]
48	Xuemei Xi	[17] [20]
49	Weize Xie	[12] [14]

Colors in the list of coauthors