Juinn-Dar Huang

	2009
17		Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang: Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. ASP-DAC 2009: 19-24
16		Chia-I Chen, Juinn-Dar Huang: CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. ASP-DAC 2009: 67-72
15		Yu-Ru Hong, Juinn-Dar Huang: Reducing fault dictionary size for million-gate large circuits. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
	2008
14		Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang: A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. ASP-DAC 2008: 16-21
13		Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou: Verification of Pin-Accurate Port Connections. IEEE Design & Test of Computers 25(5): 478-486 (2008)
	2007
12		Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou: A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. ASP-DAC 2007: 165-170
11		Yu-Ru Hong, Juinn-Dar Huang: Fault Dictionary Size Reduction for Million-Gate Large Circuits. ASP-DAC 2007: 829-834
	2006
10		Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: FSM-based transaction-level functional coverage for interface compliance verification. ASP-DAC 2006: 448-453
9		Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou: A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. ASP-DAC 2006: 600-605
	2004
8		Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang: Verification on Port Connections. ITC 2004: 830-836
	2001
7		Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang: Unified functional decomposition via encoding for FPGA technology mapping. IEEE Trans. VLSI Syst. 9(2): 251-260 (2001)
	2000
6		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans. VLSI Syst. 8(4): 392-400 (2000)
	1998
5		Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang: Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. DAC 1998: 712-717
4		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang: On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. VLSI Syst. 6(4): 634-642 (1998)
	1996
3		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ICCAD 1996: 13-17
	1995
2		Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao: Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. DAC 1995: 65-69
1		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. ICCAD 1995: 359-363

Coauthor Index

1	Shih-Min Chao	[2]
2	Chia-I Chen	[16]
3	Chien-Hua Chen	[9]
4	Hsien-Ho Chuang	[4]
5	Yu-Ju Hong	[17]
6	Yu-Ru Hong	[11] [14] [15]
7	Wei-Sheng Huang	[14]
8	Ya-Shih Huang	[14] [17]
9	Jie-Hong Roland Jiang	[5] [7]
10	Jing-Yang Jou	[1] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13]
11	Geeng-Wei Lee	[8] [9] [12] [13]
12	Bu-Ching Lin	[12]
13	Wen-Zen Shen	[1] [2] [3] [4] [6]
14	Che-Hua Shih	[10]
15	Man-Yun Su	[10]
16	Chun-Yao Wang	[8] [13]

Colors in the list of coauthors