Zhangcai Huang

	2009
16		Zhangcai Huang, Minglu Jiang, Yasuaki Inoue: A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback. IEICE Transactions 92-C(6): 806-814 (2009)
	2007
15		Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue: Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies. ASP-DAC 2007: 565-570
14		Hong Yu, Yasuaki Inoue, Kazutoshi Sako, Xiaochuan Hu, Zhangcai Huang: An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm. IEICE Transactions 90-A(10): 2124-2131 (2007)
13		Zhangcai Huang, Yasuaki Inoue, Hong Yu, Jun Pan, Yun Yang, Quan Zhang, Shuai Fang: Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System. IEICE Transactions 90-A(4): 732-740 (2007)
12		Jun Pan, Yasuaki Inoue, Zheng Liang, Zhangcai Huang, Weilun Huang: A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect. IEICE Transactions 90-A(4): 748-755 (2007)
	2006
11		Zhangcai Huang, Yasuaki Inoue, Hong Yu, Quan Zhang: A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback. APCCAS 2006: 708-711
10		Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang: An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits. ISCAS 2006
9		Zhangcai Huang, Yasuaki Inoue, Quan Zhang, Yuehu Zhou, Long Xie, Harutoshi Ogai: Behavioral macromodeling of analog LSI implementation for automobile intake system. ISCAS 2006
8		Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang: An Effective Pseudo-Transient Algorithm for Finding Dc Solutions of Nonlinear Circuits. IEICE Transactions 89-A(10): 2724-2731 (2006)
7		Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue: Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay. IEICE Transactions 89-A(4): 840-846 (2006)
6		Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda: Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. IEICE Transactions 89-A(4): 847-855 (2006)
5		Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue: Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays. IEICE Transactions 89-A(4): 856-864 (2006)
	2005
4		Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue: Effective capacitance for gate delay with RC loads. ISCAS (3) 2005: 2795-2798
3		Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao: A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads. IEICE Transactions 88-A(10): 2562-2569 (2005)
2		Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue: Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew. IEICE Transactions 88-A(12): 3367-3374 (2005)
1		Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda: Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Transactions 88-A(12): 3453-3462 (2005)

Coauthor Index

1	Shuai Fang	[13]
2	Junko Fujii	[5]
3	Masanori Hashimoto	[1]
4	Xiaochuan Hu	[14]
5	Weilun Huang	[12]
6	Ryosuke Inagaki	[1]
7	Toshinori Inoshita	[5]
8	Yasuaki Inoue	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
9	Minglu Jiang	[16]
10	Toshiki Kanamoto	[6]
11	Akira Kasebe	[1] [5] [6]
12	Atsushi Kurokawa	[1] [2] [3] [4] [5] [6] [7] [15]
13	Zheng Liang	[12]
14	Junfa Mao	[3]
15	Hiroo Masuda	[1] [5] [6]
16	Yuki Matsuya	[8] [10]
17	Harutoshi Ogai	[9]
18	Jun Pan	[2] [12] [13]
19	Kazutoshi Sako	[14]
20	Long Xie	[9]
21	Yun Yang	[1] [6] [7] [13]
22	Hong Yu	[7] [8] [10] [11] [13] [14] [15]
23	Quan Zhang	[9] [11] [13]
24	Yuehu Zhou	[9]