Wei Hwang

	2008
27		Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang: "Green" micro-architecture and circuit co-design for ternary content addressable memory. ISCAS 2008: 3322-3325
26		Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang: A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. ISCAS 2008: 3342-3345
25		Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang: Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. NOCS 2008: 77-83
24		Mu-Tien Chang, Po-Tsang Huang, Wei Hwang: A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC 2008: 175-178
23		Wei-Chih Hsieh, Wei Hwang: In-situ self-aware adaptive power control system with multi-mode power gating network. SoCC 2008: 215-218
22		Hao-I Yang, Ssu-Yun Lai, Wei Hwang: Low-power floating bitline 8-T SRAM design with write assistant circuits. SoCC 2008: 239-242
21		Ming-Hung Chang, Li-Pu Chuang, I-Ming Chang, Wei Hwang: A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. SoCC 2008: 97-100
	2007
20		Ming-Hung Chang, Zong-Xi Yang, Wei Hwang: A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. ISCAS 2007: 1137-1140
19		Wei-Chih Hsieh, Wei Hwang: Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control. ISCAS 2007: 1637-1640
	2006
18		Po-Tsang Huang, Wei-Keng Chang, Wei Hwang: Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. APCCAS 2006: 1301-1304
17		Chi-Chen Lai, Wei Hwang: A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor. APCCAS 2006: 1931-1934
16		Jen-Wei Yang, Po-Tsang Huang, Wei Hwang: On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. APCCAS 2006: 666-669
15		Po-Tsang Huang, Wei Hwang: 2-level FIFO architecture design for switch fabrics in network-on-chip. ISCAS 2006
14		Tzu-Chiang Chao, Wei Hwang: A 1.7mW all digital phase-locked loop with new gain generator and low power DCO. ISCAS 2006
13		Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang: A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM. ISCAS 2006
	2005
12		Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen: Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. ISCAS (1) 2005: 444-447
	2004
11		Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang: Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. VLSI Signal Processing 38(2): 101-113 (2004)
	2003
10		Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban: Low-power circuits and technology for wireless digital systems. IBM Journal of Research and Development 47(2-3): 283-298 (2003)
	2001
9		Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang: SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI 2001: 37-42
8		W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi: Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED 2001: 263-266
7		Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann: Design Of Provably Correct Storage Arrays. VLSI Design 2001: 196-
	2000
6		George Gristede, Wei Hwang: A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. ACM Great Lakes Symposium on VLSI 2000: 101-106
5		Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang: "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED 2000: 203-206
4		Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang: A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design 2000: 44-49
	1999
3		Rajiv V. Joshi, Wei Hwang: Design Considerations and Implementation of a High Performance Dynamic Register File. VLSI Design 1999: 526-531
	1997
2		W. K. Luk, Y. Katayama, Wei Hwang, Matthew R. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi: Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285
1		Wei Hwang, Rajiv V. Joshi, Walter H. Henkels: A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. ICCD 1997: 712-717

Coauthor Index

1	Azeez J. Bhavnagarwala	[10]
2	I-Ming Chang	[21]
3	Ming-Hung Chang	[20] [21] [26]
4	Mu-Tien Chang	[24]
5	Shu-Wei Chang	[27]
6	Wei-Keng Chang	[18]
7	Tzu-Chiang Chao	[14]
8	Chih-Kai Chen	[12]
9	W. Chen	[8]
10	Kenneth Chin	[10]
11	Shu-Shin Chin	[11]
12	Ching-Te Chuang	[4] [5] [9]
13	Li-Pu Chuang	[21] [26]
14	B. El-Kareh	[2]
15	Wei-Li Fang	[25]
16	George Gristede	[6] [8] [10]
17	Anne-Marie Haen	[10]
18	Walter H. Henkels	[1]
19	Sangjin Hong	[11]
20	Wei-Chih Hsieh	[19] [23]
21	Chung-Hsien Hua	[12] [13]
22	Po-Tsang Huang	[15] [16] [18] [24] [25] [26] [27]
23	Rajiv V. Joshi	[1] [2] [3] [4] [5] [7] [8] [9]
24	Chih-Hao Kan	[26]
25	Y. Katayama	[2]
26	Mark B. Ketchen	[10]
27	Suhwan Kim	[10] [11]
28	T. Kirihata	[2]
29	Daniel R. Knebel	[10]
30	Stephen V. Kosonocky	[8] [10]
31	Prabhakar Kudva	[8]
32	Andreas Kuehlmann	[7]
33	Chi-Chen Lai	[17]
34	Ssu-Yun Lai	[22]
35	Wen-Yen Liu	[27]
36	W. K. Luk	[2]
37	Seiji Munetoh	[2]
38	Chi-Wei Peng	[13]
39	Akashi Satoh	[2]
40	Ghavam V. Shahidi	[4]
41	Yin-Ling Wang	[25]
42	Kevin W. Warren	[10]
43	S. C. Wilson	[4] [5]
44	H. Wong	[2]
45	Matthew R. Wordeman	[2]
46	P. Xiao	[2]
47	Hao-I Yang	[22]
48	Jen-Wei Yang	[16]
49	Zong-Xi Yang	[20]
50	Victor V. Zyuban	[10]

Colors in the list of coauthors