Paolo Ienne

	2009
76		Amit Verma, Ajay K. Verma, Philip Brisk, Paolo Ienne: Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC 2009: 203-209
75		Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne: A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219
74		Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon: Way Stealing: cache-assisted automatic instruction set extensions. DAC 2009: 31-36
73		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj: 3D configuration caching for 2D FPGAs. FPGA 2009: 286
72		Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne: MPSoC Design Using Application-Specific Architecturally Visible Communication. HiPEAC 2009: 183-197
71		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed Hosein Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. TRETS 2(2): (2009)
70		Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne: Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Transactions on Computational Science 4: 230-243 (2009)
	2008
69		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Efficient synthesis of compressor trees on FPGAs. ASP-DAC 2008: 138-143
68		Ajay K. Verma, Philip Brisk, Paolo Ienne: Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC 2008: 334-339
67		Seyed Hosein Attarzadeh Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Design space exploration for field programmable compressor trees. CASES 2008: 207-216
66		Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon: Speculative DMA for architecturally visible storage in instruction set extensions. CODES+ISSS 2008: 243-248
65		Ajay K. Verma, Philip Brisk, Paolo Ienne: Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE 2008: 1250-1255
64		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE 2008: 1256-1261
63		Francesco Regazzoni, Thomas Eisenbarth, Luca Breveglieri, Paolo Ienne, Israel Koren: Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?. DFT 2008: 202-210
62		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: A novel FPGA logic block for improved arithmetic performance. FPGA 2008: 171-180
61		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190
60		Maurizio Skerlj, Paolo Ienne: Error Protected Data Bus Inversion Using Standard DRAM Components. ISQED 2008: 35-42
59		Paolo Ienne, P. Petrov: Guest Editorial Special Section on Application Specific Processors. IEEE Trans. VLSI Syst. 16(10): 1257-1258 (2008)
58		Ajay K. Verma, Philip Brisk, Paolo Ienne: Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1761-1774 (2008)
	2007
57		Ajay K. Verma, Paolo Ienne: Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. ASP-DAC 2007: 601-608
56		Ajay K. Verma, Philip Brisk, Paolo Ienne: Rethinking custom ISE identification: a new processor-agnostic method. CASES 2007: 125-134
55		Philip Brisk, Ajay K. Verma, Paolo Ienne: An optimistic and conservative register assignment heuristic for chordal graphs. CASES 2007: 209-217
54		Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar: Enhancing FPGA Performance for Arithmetic Circuits. DAC 2007: 334-337
53		Ajay K. Verma, Philip Brisk, Paolo Ienne: Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC 2007: 404-409
52		Ajay K. Verma, Paolo Ienne: Automatic synthesis of compressor trees: reevaluating large counters. DATE 2007: 443-448
51		Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar: Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. DFT 2007: 508-516
50		Philip Brisk, Ajay K. Verma, Paolo Ienne: Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD 2007: 172-179
49		Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne: A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. ICSAMOS 2007: 209-214
48		Frederic Worm, Patrick Thiran, Paolo Ienne: Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs. ISQED 2007: 861-866
47		Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement CoRR abs/0710.4820: (2007)
46		Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: Introduction of Architecturally Visible Storage in Instruction Set Extensions. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 435-446 (2007)
	2006
45		Ajay K. Verma, Paolo Ienne: Towards the automatic exploration of arithmetic-circuit architectures. DAC 2006: 445-450
44		Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi: Automatic identification of application-specific functional units with architecturally visible storage. DATE 2006: 212-217
43		Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma: Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. DATE 2006: 218-223
42		Frederic Worm, Patrick Thiran, Paolo Ienne: Designing Robust Checkers in the Presence of Massive Timing Errors. IOLTS 2006: 281-286
41		Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi: Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. VLSI Design 2006: 651-656
40		Derin Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici: A Predictable Communication Scheme for Embedded Multiprocessor Systems. VLSI-SoC 2006: 152-157
39		Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. IEEE Trans. VLSI Syst. 14(7): 754-762 (2006)
38		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Virtual memory window for application-specific reconfigurable coprocessors. IEEE Trans. VLSI Syst. 14(8): 910-915 (2006)
37		Laura Pozzi, Kubilay Atasu, Paolo Ienne: Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1209-1229 (2006)
	2005
36		Frederic Worm, Patrick Thiran, Paolo Ienne: A Unified Coding Framework for Delay-Insensitivity. ASYNC 2005: 201-211
35		Laura Pozzi, Paolo Ienne: Exploiting pipelining to relax register-file port constraints of instruction-set extensions. CASES 2005: 2-10
34		Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne: Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. CODES+ISSS 2005: 243-248
33		Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. DATE 2005: 1246-1251
32		Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici: Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. ESTImedia 2005: 135-140
31		Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne: Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. ISCAS (2) 2005: 1782-1785
30		Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli: Self-calibrating networks-on-chip. ISCAS (3) 2005: 2361-2364
29		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Seamless Hardware-Software Integration in Reconfigurable Computing Systems. IEEE Design & Test of Computers 22(2): 102-113 (2005)
28		Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli: A robust self-calibrating transmission scheme for on-chip networks. IEEE Trans. VLSI Syst. 13(1): 126-139 (2005)
	2004
27		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. ASAP 2004: 339-351
26		Marc Epalza, Paolo Ienne, Daniel Mlynek: Dynamic Reallocation of Functional Units in Superscalar Processors. Asia-Pacific Computer Systems Architecture Conference 2004: 185-198
25		Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil Dutt: Introduction of local memory elements in instruction set extensions. DAC 2004: 729-734
24		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Virtual memory window for application-specific reconfigurable coprocessors. DAC 2004: 948-953
23		Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne: Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. DATE 2004: 748
22		Paolo Ienne, Ajay K. Verma: Arithmetic Transformations to Maximise the Use of Compressor Trees. DELTA 2004: 219-224
21		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. FCCM 2004: 24-33
20		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. FPL 2004: 596-605
19		Frederic Worm, Paolo Ienne, Patrick Thiran: Soft self-synchronising codes for self-calibrating communication. ICCAD 2004: 440-447
18		Ajay K. Verma, Paolo Ienne: Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. ICCAD 2004: 791-798
17		Marc Epalza, Paolo Ienne, Daniel Mlynek: Adding Limited Reconfigurability to Superscalar Processors. IEEE PACT 2004: 53-62
16		Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne: Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. SCOPES 2004: 17-32
15		Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli: On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations. IEEE Design & Test of Computers 21(6): 524-535 (2004)
	2003
14		Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli: Automatic Instruction Set Extension and Utilization for Embedded Processors. ASAP 2003: 108-
13		Kubilay Atasu, Laura Pozzi, Paolo Ienne: Automatic application-specific instruction-set extensions under microarchitectural constraints. DAC 2003: 256-261
12		Kubilay Atasu, Laura Pozzi, Paolo Ienne: Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. International Journal of Parallel Programming 31(6): 411-428 (2003)
	2002
11		Laura Pozzi, Miljan Vuletic, Paolo Ienne: Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. DATE 2002: 1138
10		M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha: A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ISSS 2002: 2-7
9		Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm: An Adaptive Low-Power Transmission Scheme for On-Chip Networks. ISSS 2002: 92-100
	1998
8		Paolo Ienne, Alexander Grießing: Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? DAC 1998: 396-401
	1997
7		Paolo Ienne: Digital Connectionist Hardware: Current Problems and Future Challenges. IWANN 1997: 688-713
	1996
6		Thierry Cornu, Paolo Ienne, Dagmar Niebur, Patrick Thiran, Marc A. Viredaz: Design, Implementation, and Test of a Multi-Model Systolic Neural-Network Accelerator. Scientific Programming 5(1): 47-61 (1996)
5		Paolo Ienne, Thierry Cornu, Gary Kuhn: Special-purpose digital hardware for neural networks: An architectural survey. VLSI Signal Processing 13(1): 5-25 (1996)
	1995
4		Paolo Ienne: Horizontal Microcode Compaction for Programmable Systolic Accelerators. ASAP 1995: 85-
3		Paolo Ienne, Marc A. Viredaz: GENES IV: A bit-serial processing element for a multi-model neural-network accelerator. VLSI Signal Processing 9(3): 257-273 (1995)
	1994
2		Paolo Ienne, Marc A. Viredaz: Bit-Serial Multipliers and Squarers. IEEE Trans. Computers 43(12): 1445-1450 (1994)
	1993
1		Francesco Mondada, Edoardo Franzi, Paolo Ienne: Mobile Robot Miniaturisation: A Tool for Investigation in Control Algorithms. ISER 1993: 501-513

Coauthor Index

1	Kubilay Atasu	[12] [13] [25] [37]
2	Panagiotis Athanasopoulos	[61] [71] [73]
3	Stéphane Badel	[49] [75]
4	M. Balakrishnan	[10]
5	Sudarshan Banerjee	[33] [39] [41] [47]
6	Partha Biswas	[25] [33] [39] [41] [44] [46] [47]
7	Luca Breveglieri	[51] [63]
8	Philip Brisk	[50] [53] [54] [55] [56] [58] [61] [62] [64] [65] [66] [67] [68] [69] [71] [72] [73] [74] [75] [76]
9	Alessandro Cevrero	[61] [67] [71] [73] [75]
10	Edoardo Charbon	[66] [72] [74]
11	Vinay Choudhary	[25]
12	Thierry Cornu	[5] [6]
13	Alper Demir	[32]
14	Zeynep Toprak Deniz	[49] [70]
15	Christophe Dubach	[34]
16	Nikil D. Dutt (Nikil Dutt)	[25] [33] [39] [41] [44] [46] [47]
17	Thomas Eisenbarth	[49] [51] [63] [70]
18	Marc Epalza	[17] [26]
19	Nuria Pazos Escudero	[31]
20	Edoardo Franzi	[1]
21	Anup Gangwar	[10]
22	Alexander Grießing	[8]
23	Johann Großschädl	[43] [49] [51] [70]
24	Frank K. Gürkaynak	[61] [67] [70] [71]
25	Derin Derin Harmanci	[40]
26	Mehmet Derin Harmanci	[31]
27	Diviya Jain	[16]
28	Theo Kluter	[66] [72] [74] [75]
29	Israel Koren	[51] [63]
30	Gary Kuhn	[5]
31	Anshul Kumar	[10] [16]
32	Yusuf Leblebici	[31] [32] [40] [49] [61] [67] [70] [71] [73] [75]
33	Marco Macchetti	[49] [70]
34	Giovanni De Micheli	[9] [14] [15] [28] [30]
35	Bhuvan Middha	[10]
36	Daniel Mlynek	[17] [26]
37	Francesco Mondada	[1]
38	Seyed Hosein Attarzadeh Niaki	[67] [71]
39	Chrysostomos Nicopoulos	[67] [71]
40	Dagmar Niebur	[6]
41	Christof Paar	[49] [51] [70]
42	Hadi Parandeh-Afshar	[54] [61] [62] [64] [69] [71] [73]
43	Nuria Pazos	[40]
44	P. Petrov	[59]
45	Armita Peymandoust	[14]
46	Axel Poschmann	[49] [70]
47	Laura Pozzi	[11] [12] [13] [14] [16] [20] [21] [23] [24] [25] [27] [29] [33] [34] [35] [37] [38] [39] [41] [43] [44] [46] [47] [49] [70]
48	Francesco Regazzoni	[49] [51] [63] [70] [75]
49	Ludovic Righetti	[23]
50	Maurizio Skerlj	[60] [73]
51	François-Xavier Standaert	[75]
52	Serdar Tasiran	[32]
53	Patrick Thiran	[6] [9] [15] [19] [28] [30] [36] [42] [48]
54	Stefan Tillich	[43]
55	Ajay K. Verma	[18] [22] [43] [45] [50] [52] [53] [54] [55] [56] [57] [58] [61] [65] [68] [71] [76]
56	Amit Verma	[76]
57	Marc A. Viredaz	[2] [3] [6]
58	Miljan Vuletic	[11] [20] [21] [23] [24] [27] [29] [34] [38]
59	Frederic Worm	[9] [15] [19] [28] [30] [36] [42] [48]
60	Soner Yaldiz	[32]

Colors in the list of coauthors