Masaharu Imai

	2009
40		Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. ASP-DAC 2009: 449-454
39		Hassan A. Youness, Keishi Sakanushi, Yoshinori Takeuchi, Ashraf Salem, Abdel-Moneim Wahdan, Masaharu Imai: Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems. IEICE Transactions 92-A(4): 1088-1095 (2009)
38		Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai: Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors. IEICE Transactions 92-A(4): 1161-1173 (2009)
	2008
37		Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai: Operation shuffling over cycle boundaries for low energy L0 clustering. ASAP 2008: 150-155
36		Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai: Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling. IEICE Transactions 91-A(2): 604-612 (2008)
	2007
35		Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. ASP-DAC 2007: 286-291
34		Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: A low power VLIW processor generation method by means of extracting non-redundant activation conditions. CODES+ISSS 2007: 227-232
33		Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai: Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
32		M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC CoRR abs/0710.4746: (2007)
31		Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto: Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram. IEICE Transactions 90-A(12): 2800-2809 (2007)
	2006
30		Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa: Pack instruction generation for media pUsing multi-valued decision diagram. CODES+ISSS 2006: 154-159
29		Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. VLSI-SoC 2006: 290-295
	2005
28		Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic: Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005 CSREA Press 2005
27		M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Enabling RTOS simulation modeling in a system level design language. ASP-DAC 2005: 936-939
26		Masaharu Imai, Akira Kitajima: Verification Challenges in Configurable Processor Design with ASIP Meister. CHARME 2005: 2
25		M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. DATE 2005: 554-559
24		Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai: Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. ESTImedia 2005: 81-86
	2004
23		Masaharu Imai: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 IEEE 2004
22		Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Synthesizable HDL generation method for configurable VLIW processors. ASP-DAC 2004: 842-845
21		Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Architecture-Level Performance Estimation for IP-Based Embedded Systems. DATE 2004: 1002-1007
20		H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation. ICDCS Workshops 2004: 824-830
19		Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai: S-sequence: a new floorplan representation method preserving room abutment relationships. ISCAS (4) 2004: 505-508
	2003
18		Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai: A Code Selection Method for SIMD Processors with PACK Instructions. SCOPES 2003: 66-80
	2002
17		Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai: Design of Application Specific CISC Using PEAS-III. IEEE International Workshop on Rapid System Prototyping 2002: 12-17
	2001
16		Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai: Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. ASP-DAC 2001: 649-654
15		Hideki Yamauchi, Yoshinori Takeuchi, Masaharu Imai: VLSI Implementation of Fractal Image Compression Processor for Moving Pictures. EUROMICRO 2001: 400-409
	2000
14		Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura: One language or more?: how can we design an SoC at a system level? ASP-DAC 2000: 653-654
13		Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi: PEAS-III: An ASIP Design Environment. ICCD 2000: 430-436
	1999
12		Eiichirou Shigehara, Yoshinori Takeuchi, Masaharu Imai, Tsutomu Kimura: Application of FHM-Based Design Method to Scalable 2-D DCT Processor. EUROMICRO 1999: 1406-1409
	1998
11		Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi: A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. ASP-DAC 1998: 367-372
	1996
10		Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi: A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. DAC 1996: 527-532
9		Masaharu Imai, Eugenio Villar: ASPDAC 1995: HDL synthesizability and interoperability. IEEE Design & Test of Computers 13(1): 3-4 (1996)
	1995
8		Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi: A hardware/software codesign method for pipelined instruction set processor using adaptive database. ASP-DAC 1995
7		Masaharu Imai, Eugenio Villar: Future direction of synthesizability and interoperability of HDL's: part 1. ASP-DAC 1995
6		Eugenio Villar, Masaharu Imai: Future direction of synthesizabilty and interoperability of HDL's: part 2. ASP-DAC 1995
5		Binh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi: A hardware/software partitioning algorithm for pipelined instruction set processor. EURO-DAC 1995: 176-181
	1993
4		Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi: An ASIP instruction set optimization algorithm with functional module sharing constraint. ICCAD 1993: 526-532
	1991
3		Jun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi: An Integrated Design Environment for Application Specific Integrated Processor. ICCD 1991: 414-417
	1986
2		Hajime Miura, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki: Implementation of Parallel Prolog on Tree Machines. FJCC 1986: 287-296
	1984
1		Masaharu Imai, Yuuji Tateizumi, Yuuji Yoshida, Teruo Fukumura: The Architecture and Efficiency of DON: A Combinatorial Problem Oriented Multicomputer System. ICDCS 1984: 174-182

Coauthor Index

1	H. M. AbdElSalam	[20]
2	Masaaki Abe	[35]
3	Alauddin Alomary	[4]
4	Alauddin Y. Alomary	[3]
5	Hamid R. Arabnia	[28]
6	Karen Bartleson	[14]
7	Jürgen Becker	[28]
8	Nguyen-Ngoc Bình	[8] [10] [11]
9	Francky Catthoor	[24] [33] [36] [37] [38] [40]
10	Peter Flake	[14]
11	Teruo Fukumura	[1]
12	Daniel Gajski (Daniel D. Gajski)	[14]
13	Tetsuya Hakata	[3]
14	M. Abdelsalam Hassan	[25] [27] [32]
15	Shigeaki Higaki	[13]
16	Nobuyuki Hikichi	[3] [4] [5] [8] [10]
17	Yoshimichi Honma	[4]
18	Toshihide Ibaraki	[2]
19	Yohei Ishimaru	[19]
20	Makiko Itoh	[13] [16]
21	Hirofumi Iwato	[34]
22	Murali Jayapala	[24] [33] [36] [37] [38] [40]
23	Tsutomu Kimura	[12]
24	Akira Kitajima	[13] [16] [17] [26]
25	Shinsuke Kobayashi	[18] [19] [20] [22]
26	Yuki Kobayashi	[22] [24] [33] [36] [37]
27	Nobu Matsumoto	[30] [31]
28	Hajime Miura	[2]
29	Masaki Nakagawa	[30]
30	Takeharu Nakata	[4]
31	Binh Ngoc Nguyen	[5]
32	Koji Okuda	[22]
33	Yutaka Ota	[30] [31]
34	Praveen Raghavan	[24] [33] [36] [37] [38] [40]
35	Wolfgang Rosenstiel	[14]
36	Keishi Sakanushi	[18] [19] [20] [21] [22] [25] [27] [29] [30] [31] [32] [34] [35] [39] [40]
37	Zoran A. Salcic (Zoran Salcic)	[28]
38	Ashraf Salem	[39]
39	Toshiyuki Sasaki	[17]
40	Jun Sato	[3] [13] [16]
41	Steven Schulz	[14]
42	Eiichirou Shigehara	[12]
43	Akichika Shiomi	[8] [10] [13] [16]
44	Takeshi Shiro	[35]
45	Gary Smith	[14]
46	Hiroki Tagawa	[31]
47	Yoshinori Takeuchi	[11] [12] [13] [15] [16] [17] [18] [19] [20] [21] [22] [25] [27] [29] [30] [31] [32] [34] [35] [38] [39] [40]
48	Hiroaki Tanaka	[18] [30] [31]
49	Ittetsu Taniguchi	[29] [38] [40]
50	Yuuji Tateizumi	[1]
51	Kyoko Ueda	[21] [29]
52	Eugenio Villar	[6] [7] [9]
53	Abdel-Moneim Wahdan	[39]
54	Masafumi Yamashita	[2]
55	Hideki Yamauchi	[15]
56	Laurence Tianruo Yang	[28]
57	Hiroto Yasuura	[14]
58	Yuuji Yoshida	[1]
59	Hassan A. Youness	[39]

Colors in the list of coauthors