Masashi Imai Coauthor index DBLP Vis pubzone.org

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17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKimiyoshi Usami, Toshiaki Shirai, Tasunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura: Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386
2008
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasashi Imai, Takashi Nanya: A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. ACSD 2008: 21-26
2007
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRyo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya: Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. DATE 2007: 797-802
2006
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasashi Imai, Takashi Nanya: A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ASYNC 2006: 68-77
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya: Design Method of High Performance and Low Power Functional Units Considering Delay Variations. IEICE Transactions 89-A(12): 3519-3528 (2006)
2004
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasashi Imai, Metehan Özcan, Takashi Nanya: Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. ASYNC 2004: 62-71
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasayuki Tsukisaka, Masashi Imai, Takashi Nanya: Asynchronous Scan-Latch controller for Low Area Overhead DFT. ICCD 2004: 66-71
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya: Skewed Checkpointing for Tolerating Multi-Node Failures. SRDS 2004: 116-125
2003
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya: Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. ASYNC 2003: 184-195
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya: A zero-time-overhead asynchronous four-phase controller. ISCAS (5) 2003: 205-208
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya: Control signal sharing of asynchronous circuits using datapath delay information. ISCAS (5) 2003: 617-620
2002
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLT. Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura: Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. APCCAS (1) 2002: 211-216
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMetehan Özcan, Masashi Imai, Takashi Nanya: Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. ASYNC 2002: 109-114
4no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasayuki Tsukisaka, Masashi Imai, Takashi Nanya: High Throughput Asynchronous Domino Using Dual output Buffer. IWLS 2002: 279-282
2001
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMotokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno: Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ASYNC 2001: 162-172
1998
2no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAkihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya: TITAC-2: An Asynchronous 32-bit Microprocessor. ASP-DAC 1998: 319-320
1997
1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAkihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya: TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. ICCD 1997: 288-294

Coauthor Index

1Hideharu Amano [17]
2Taro Fujii [1] [2]
3Izumi Fukasaku [1] [2]
4Tasunori Hashida [17]
5Takuro Hayashida [10]
6Euiseok Kim [7] [8] [9]
7Masaaki Kondo [6] [10] [13] [15] [17]
8Masashi Kuwako [1] [2]
9Hiroki Masuda [17]
10Hiroshi Nakamura [3] [6] [7] [8] [9] [10] [13] [15] [17]
11Mitsutaka Nakata [17]
12Mitaro Namiki [17]
13Takashi Nanya [1] [2] [3] [4] [5] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
14T. Ohneda [6]
15Motokazu Ozawa [1] [2] [3]
16Metehan Özcan [5] [8] [12]
17Hiroshi Saito [7] [8] [9]
18Naomi Seki [17]
19Toshiaki Shirai [17]
20Nattha Sretasereekul [7] [8] [9]
21Yuya Tajima [10]
22Akihiro Takamura [1] [2]
23Seidai Takeda [17]
24K. Thongnoo [8]
25Masayuki Tsukisaka [4] [11]
26Yoichiro Ueno [1] [2] [3]
27Kimiyoshi Usami [17]
28Kouichi Watanabe [13]
29Ryo Watanabe [15]

Copyright © Sat Nov 14 20:26:04 2009 by Michael Ley (ley@uni-trier.de)