| 2009 | ||
|---|---|---|
| 37 | Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki Murakami: A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. ASP-DAC 2009: 564-569 | |
| 36 | Takatsugu Ono, Koji Inoue, Kazuaki Murakami, Kenji Yoshida: Reducing On-Chip DRAM Energy via Data Transfer Size Optimization. IEICE Transactions 92-C(4): 433-443 (2009) | |
| 2008 | ||
| 35 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Design space exploration for a coarse grain accelerator. ASP-DAC 2008: 685-690 | |
| 34 | Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue: Improved Policies for Drowsy Caches in Embedded Processors. DELTA 2008: 362-367 | |
| 33 | Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami: Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. ISLPED 2008: 241-246 | |
| 32 | Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. ISVLSI 2008: 363-368 | |
| 31 | Ryutaro Susukita, Hisashige Ando, Mutsumi Aoyagi, Hiroaki Honda, Yuichi Inadomi, Koji Inoue, Shigeru Ishizuki, Yasunori Kimura, Hidemi Komatsu, Motoyoshi Kurokawa, Kazuaki Murakami, Hidetomo Shibamura, Shuji Yamamura, Yunqing Yu: Performance prediction of large-scale parallell system and application using macro-level simulation. SC 2008: 20 | |
| 30 | Naofumi Takagi, Kazuaki Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda: Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits. IEICE Transactions 91-C(3): 350-355 (2008) | |
| 29 | Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems. IEICE Transactions 91-C(4): 418-431 (2008) | |
| 28 | Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami: A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions. IEICE Transactions 91-C(4): 497-508 (2008) | |
| 27 | Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: An architecture framework for an adaptive extensible processor. The Journal of Supercomputing 45(3): 313-340 (2008) | |
| 2007 | ||
| 26 | Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: The effect of temperature on cache size tuning for low energy embedded systems. ACM Great Lakes Symposium on VLSI 2007: 453-456 | |
| 25 | Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Maziar Goudarzi: Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. DATE 2007: 325-330 | |
| 24 | Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems. ESA 2007: 169-176 | |
| 23 | Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ICESS 2007: 249-260 | |
| 22 | Toshiya Takami, Jun Maki, Jun-ichi Ooba, Yuichi Inadomi, Hiroaki Honda, Ryutaro Susukita, Koji Inoue, Taizo Kobayashi, Rie Nogita, Mutsumi Aoyagi: Multi-physics Extension of OpenFMO Framework CoRR abs/0707.2630: (2007) | |
| 21 | Mariko Sakamoto, Akira Katsuno, Go Sugizaki, Toshio Yoshida, Aiichiro Inoue, Koji Inoue, Kazuaki Murakami: A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips. IEICE Transactions 90-C(10): 1972-1982 (2007) | |
| 20 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. IEICE Transactions 90-D(12): 1956-1966 (2007) | |
| 2006 | ||
| 19 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue: An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference 2006: 219-230 | |
| 18 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi: Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC 2006: 722-731 | |
| 17 | Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. FPL 2006: 1-4 | |
| 16 | Koji Inoue: Return Address Protection on Cache Memories. IEICE Transactions 89-C(12): 1937-1947 (2006) | |
| 2005 | ||
| 15 | Shigeharu Matsusaka, Koji Inoue: A Cost Effective Spacial Redundancy with Data-Path Partitioning. ICITA (2) 2005: 51-56 | |
| 14 | Hidekazu Tanaka, Koji Inoue: Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy. IEICE Transactions 88-A(12): 3274-3281 (2005) | |
| 13 | Reiko Komiya, Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches. IEICE Transactions 88-A(4): 862-868 (2005) | |
| 12 | Koji Inoue: Energy-security tradeoff in a secure cache architecture against buffer overflow attacks. SIGARCH Computer Architecture News 33(1): 81-89 (2005) | |
| 2003 | ||
| 11 | Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga: Reducing Access Count to Register-Files through Operand Reuse. Asia-Pacific Computer Systems Architecture Conference 2003: 112-121 | |
| 2002 | ||
| 10 | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Reducing power consumption of instruction ROMs by exploiting instruction frequency. APCCAS (2) 2002: 1-6 | |
| 9 | Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue: Multiplier energy reduction through bypassing of partial products. APCCAS (2) 2002: 13-17 | |
| 8 | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A Low Energy Set-Associative I-Cache with Extended BTB. ICCD 2002: 187- | |
| 7 | Vasily G. Moshnyaga, Koji Inoue, Mizuka Fukagawa: Reducing energy consumption of video memory by bit-width compression. ISLPED 2002: 142-147 | |
| 6 | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A history-based I-cache for low-energy multimedia applications. ISLPED 2002: 148-153 | |
| 5 | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints. PACS 2002: 18-32 | |
| 4 | Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga: Register File Energy Reduction by Operand Data Reuse. PATMOS 2002: 278-288 | |
| 2000 | ||
| 3 | Koji Inoue, Koji Kai, Kazuaki Murakami: Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. Intelligent Memory Systems 2000: 169-178 | |
| 1999 | ||
| 2 | Koji Inoue, Koji Kai, Kazuaki Murakami: Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. HPCA 1999: 218-222 | |
| 1 | Koji Inoue, Tohru Ishihara, Kazuaki Murakami: Way-predicting set-associative cache for high performance and low energy consumption. ISLPED 1999: 273-275 | |