| 2009 | ||
|---|---|---|
| 38 | Michiko Inoue, Tsuyoshi Suzuki, Hideo Fujiwara: Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms. DISC 2009: 172-173 | |
| 2008 | ||
| 37 | Seiji Kajihara, Michiko Inoue: Special Section on Test and Verification of VLSIs. IEICE Transactions 91-D(3): 640-641 (2008) | |
| 36 | Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara: Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. IEICE Transactions 91-D(3): 763-770 (2008) | |
| 2006 | ||
| 35 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. IEEE Trans. VLSI Syst. 14(11): 1203-1215 (2006) | |
| 34 | Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara: A Low Power Deterministic Test Using Scan Chain Disable Technique. IEICE Transactions 89-D(6): 1931-1939 (2006) | |
| 2005 | ||
| 33 | Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. Asian Test Symposium 2005: 254-259 | |
| 32 | Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki: Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. Asian Test Symposium 2005: 444-449 | |
| 31 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Testing Superscalar Processors in Functional Mode. FPL 2005: 747-750 | |
| 30 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-based delay fault self-testing of pipelined processor cores. ISCAS (6) 2005: 5686-5689 | |
| 29 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Delay Fault Testing of Processor Cores in Functional Mode. IEICE Transactions 88-D(3): 610-618 (2005) | |
| 28 | Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara: Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. IEICE Transactions 88-D(8): 1940-1947 (2005) | |
| 2004 | ||
| 27 | Kazuko Kambe, Michiko Inoue, Hideo Fujiwara: Efficient Template Generation for Instruction-Based Self-Test of Processor Cores. Asian Test Symposium 2004: 152-157 | |
| 26 | Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara: Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. Asian Test Symposium 2004: 32-39 | |
| 25 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-Based Delay Fault Self-Testing of Processor Cores. VLSI Design 2004: 933- | |
| 2003 | ||
| 24 | Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara: Test Synthesis for Datapaths Using Datapath-Controller Functions. Asian Test Symposium 2003: 294-299 | |
| 23 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Software-Based Delay Fault Testing of Processor Cores. Asian Test Symposium 2003: 68-71 | |
| 2002 | ||
| 22 | Michiko Inoue, Chikateru Jinno, Hideo Fujiwara: An Extended Class of Sequential Circuits with Combinational Test Generation Complexity. ICCD 2002: 200-205 | |
| 21 | Michiko Inoue, Emil Gizdarski, Hideo Fujiwara: Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. J. Electronic Testing 18(1): 55-62 (2002) | |
| 20 | Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Parallel algorithms for selection on the BSP and BSP* models. Systems and Computers in Japan 33(12): 97-107 (2002) | |
| 19 | Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A layout adjustment problem for disjoint rectangles preserving orthogonal order. Systems and Computers in Japan 33(2): 31-42 (2002) | |
| 2001 | ||
| 18 | Michiko Inoue, Shinya Umetani, Toshimitsu Masuzawa, Hideo Fujiwara: Adaptive Long-Lived O(k2)-Renaming with O(k2) Steps. DISC 2001: 123-135 | |
| 17 | Chikara Ohori, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A causal broadcast protocol for distributed mobile systems. Systems and Computers in Japan 32(3): 65-75 (2001) | |
| 2000 | ||
| 16 | Michiko Inoue, Emil Gizdarski, Hideo Fujiwara: A class of sequential circuits with combinational test generation complexity under single-fault assumption. Asian Test Symposium 2000: 398-403 | |
| 15 | Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa: Parallelizability of Some P-Complete Problems. IPDPS Workshops 2000: 116-122 | |
| 1999 | ||
| 14 | Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. Asian Test Symposium 1999: 5-12 | |
| 13 | Akihiro Fujiwara, H. Katsuki, Michiko Inoue, Toshimitsu Masuzawa: Parallel Selection Algorithms with Analysis on Clusters. ISPAN 1999: 388-393 | |
| 12 | Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model. ISPAN 1999: 394-399 | |
| 11 | Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A cost optimal parallel algorithm for weighted distance transforms. Parallel Computing 25(4): 405-416 (1999) | |
| 1998 | ||
| 10 | Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara: A High-Level Synthesis Method for Weakly Testable Data Paths. Asian Test Symposium 1998: 40-45 | |
| 9 | Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order. Graph Drawing 1998: 183-197 | |
| 8 | Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: SelfStabilizing WaitFree Clock Synchronization with Bounded Space. OPODIS 1998: 129-144 | |
| 7 | Michiko Inoue, Hideo Fujiwara: An approach to test synthesis from higher level. Integration 26(1-2): 101-116 (1998) | |
| 1997 | ||
| 6 | Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Parallel Algorithm for Weighted Distance Transforms. IPPS 1997: 407-412 | |
| 5 | Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa, Hideo Fujiwara: Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System. WDAG 1997: 290-304 | |
| 4 | Katsuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Non-scan design for testable data paths using thru operation. Systems and Computers in Japan 28(10): 60-68 (1997) | |
| 1996 | ||
| 3 | Yasuro Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Snapshot Algorithm for Distributed Mobile Systems. ICDCS 1996: 734-743 | |
| 1994 | ||
| 2 | Michiko Inoue, Wei Chen: Linear-Time Snapshot Using Multi-writer Multi-reader Registers. WDAG 1994: 130-140 | |
| 1992 | ||
| 1 | T. Yamada, Akihiro Fujiwara, Michiko Inoue: COM (Cost Oriented Memory) Testing. ITC 1992: 259 | |