Nagisa Ishiura

	2008
18		Nagisa Ishiura: Special Section on VLSI Design and CAD Algorithms. IEICE Transactions 91-A(12): 3413-3414 (2008)
17		Masanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori, Hiroyuki Kanbara, Hiroyuki Tomiyama: High-Level Synthesis of Software Function Calls. IEICE Transactions 91-A(12): 3556-3558 (2008)
	2002
16		Nagisa Ishiura, Tatsuo Watanabe: Datapath oriented codesign method of application specific DSPs using retargetable compiler. APCCAS (1) 2002: 55-58
	2000
15		Mizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe: Thread partitioning method for hardware compiler bach. ASP-DAC 2000: 303-308
	1998
14		Masayuki Yamaguchi, Nagisa Ishiura, Takashi Kambe: Binding and Scheduling Algorithms for Highly Retargetable Compilation. ASP-DAC 1998: 93-98
	1995
13		Akihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe: Optimal Scheduling for Conditional Recource Sharing. ISCAS 1995: 2297-2300
	1994
12		Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima: Fault simulation for multiple faults by Boolean function manipulation. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 531-535 (1994)
	1991
11		Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima: Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing. DAC 1991: 413-416
10		Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima: Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits. DAC 1991: 650-655
9		Nagisa Ishiura, Hiroshi Sawada, Shuzo Yajima: Minimazation of Binary Decision Diagrams Based on Exchanges of Variables. ICCAD 1991: 472-475
8		Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima: Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets. ICCAD 1991: 550-553
	1990
7		Nagisa Ishiura, Yutaka Deguchi, Shuzo Yajima: Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram. DAC 1990: 130-135
6		Shin-ichi Minato, Nagisa Ishiura, Shuzo Yajima: Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation. DAC 1990: 52-57
5		Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima: NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. DAC 1990: 8-13
4		Nagisa Ishiura, Masyuki Ito, Shuzo Yajima: Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor. IEEE Trans. on CAD of Integrated Circuits and Systems 9(8): 868-875 (1990)
	1989
3		Nagisa Ishiura, M. Takahashi, Shuzo Yajima: Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits. DAC 1989: 497-502
2		Hiroto Yasuura, Nagisa Ishiura: Semantics of a Hardware Design Language for Japanese Standardization. DAC 1989: 836-839
	1987
1		Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima: High-Speed Logic Simulation on Vector Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 6(3): 305-321 (1987)

Coauthor Index

1	Yutaka Deguchi	[7] [10]
2	Yoshiyuki Ishimori	[17]
3	Masyuki Ito	[4]
4	Takashi Kambe	[13] [14] [15]
5	Hiroyuki Kanbara	[17]
6	Shin-ichi Minato	[6]
7	Satoru Nakamura	[13]
8	Masanari Nishimura	[17]
9	Hiroyuki Ochi	[11]
10	Hiroshi Sawada	[9]
11	Isao Shirakawa	[13]
12	M. Takahashi	[3]
13	Mizuki Takahashi	[15]
14	Noriyuki Takahashi	[8] [12]
15	Hiroyuki Tomiyama	[17]
16	Tatsuo Watanabe	[16]
17	Shuzo Yajima	[1] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
18	Akihisa Yamada	[13] [15]
19	Masayuki Yamaguchi	[14]
20	Hiroto Yasuura	[1] [2] [5]

Colors in the list of coauthors