Yehea I. Ismail

	2008
90		DiaaEldin Khalil, Yehea I. Ismail: A global interconnect link design for many-core microprocessors. IFMT 2008: 14
89		Sami Kirolos, Yehia Massoud, Yehea I. Ismail: Power-supply-variation-aware timing analysis of synchronous systems. ISCAS 2008: 2418-2421
88		Sami Kirolos, Yehia Massoud, Yehea I. Ismail: Accurate analytical delay modeling of CMOS clock buffers considering power supply variations. ISCAS 2008: 3394-3397
87		Yehea I. Ismail: Interconnect design and limitations in nanoscale technologies. ISCAS 2008: 780-783
86		DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De: Analytical Model for the Propagation Delay of Through Silicon Vias. ISQED 2008: 553-556
85		D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, V. K. De: Accurate Estimation of SRAM Dynamic Stability. IEEE Trans. VLSI Syst. 16(12): 1639-1647 (2008)
84		Ja Chun Ku, Yehea I. Ismail: Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 241-248 (2008)
	2007
83		Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack: NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. ACM Great Lakes Symposium on VLSI 2007: 25-30
82		Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail: Including inductance in static timing analysis. ICCAD 2007: 686-691
81		Frank Huebbers, Ali Dasdan, Yehea I. Ismail: Multi-layer interconnect performance corners for variation-aware timing analysis. ICCAD 2007: 713-718
80		Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail: A self-adjusting clock tree architecture to cope with temperature variations. ICCAD 2007: 75-82
79		Ahmed Shebaita, Yehea I. Ismail: Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers. ISCAS 2007: 1385-1388
78		Ja Chun Ku, Yehea I. Ismail: Attaining Thermal Integrity in Nanometer Chips. ISCAS 2007: 3223-3226
77		Ja Chun Ku, Yehea I. Ismail: A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay. ISCAS 2007: 3736-3739
76		DiaaEldin Khalil, Yehea I. Ismail: Approximate Frequency Response Models for RLC Power Grids. ISCAS 2007: 3784-3787
75		Ja Chun Ku, Yehea I. Ismail: Thermal-aware methodology for repeater insertion in low-power VLSI circuits. ISLPED 2007: 86-91
74		Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail: Modeling and Characterizing Power Variability in Multicore Architectures. ISPASS 2007: 146-157
73		Serkan Ozdemir, Arindam Mallik, Ja Chun Ku, Gokhan Memik, Yehea I. Ismail: Variable latency caches for nanoscale processor. SC 2007: 20
72		Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail: Thermal Management of On-Chip Caches Through Power Density Minimization. IEEE Trans. VLSI Syst. 15(5): 592-604 (2007)
71		Ja Chun Ku, Yehea I. Ismail: Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. IEEE Trans. VLSI Syst. 15(8): 963-970 (2007)
70		Ja Chun Ku, Yehea I. Ismail: On the Scaling of Temperature-Dependent Effects. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1882-1888 (2007)
69		Shizhong Mei, Yehea I. Ismail: An Accurate Low-Iteration Algorithm for Effective Capacitance Computation. Journal of Circuits, Systems, and Computers 16(5): 791-800 (2007)
	2006
68		Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006 ACM 2006
67		Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail: Power density minimization for highly-associative caches in embedded processors. ACM Great Lakes Symposium on VLSI 2006: 100-104
66		Ja Chun Ku, Yehea I. Ismail: Area optimization for leakage reduction and thermal stability in nanometer scale technologies. ASP-DAC 2006: 231-236
65		Frank Huebbers, Ali Dasdan, Yehea I. Ismail: Computation of accurate interconnect process parameter values for performance corners under process variations. DAC 2006: 797-800
64		Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail: Importance of volume discretization of single and coupled interconnects. ICCAD 2006: 119-126
63		Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou: A timing dependent power estimation framework considering coupling. ICCAD 2006: 401-407
62		Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack: FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. ICCD 2006
61		DiaaEldin Khalil, Yehea I. Ismail: Optimum sizing of power grids for IR drop. ISCAS 2006
60		Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De: Reducing the data switching activity of serialized datastreams. ISCAS 2006
59		Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De: Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED 2006: 79-84
58		Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De: Reducing the Data Switching Activity on Serial Link Buses. ISQED 2006: 425-432
57		Masud H. Chowdhury, Yehea I. Ismail: Realistic scalability of noise in dynamic circuits. IEEE Trans. VLSI Syst. 14(6): 637-641 (2006)
56		Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De: Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 821-836 (2006)
	2005
55		John Lach, Gang Qu, Yehea I. Ismail: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005 ACM 2005
54		Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail: Physical limitations on the bit-rate of on-chip interconnects. ACM Great Lakes Symposium on VLSI 2005: 13-19
53		Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail: Statistical static timing analysis: how simple can we get? DAC 2005: 652-657
52		Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu: Piece-wise approximations of RLCK circuit responses using moment matching. DAC 2005: 927-932
51		Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail: Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. DSN 2005: 770-779
50		Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De: Serial-link bus: a low-power on-chip bus architecture. ICCAD 2005: 541-546
49		Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Expanding the frequency range of AWE via time shifting. ICCAD 2005: 935-938
48		Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail: A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD 2005: 253-257
47		Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De: Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) 2005: 592-595
46		Maged Ghoneima, Yehea I. Ismail: Accurate decoupling of capacitively coupled buses. ISCAS (4) 2005: 4146-4149
45		Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail: Thermal Management of On-Chip Caches Through Power Density Minimization. MICRO 2005: 283-293
44		Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail: Realizable reduction of interconnect circuits including self and mutual inductances. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 271-277 (2005)
43		Maged Ghoneima, Yehea I. Ismail: Optimum positioning of interleaved repeaters in bidirectional buses. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 461-469 (2005)
42		Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Weibull-based analytical waveform model. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1156-1168 (2005)
	2004
41		Yehea I. Ismail, Chirayu S. Amin: Computation of signal threshold crossing times directly from higher order moments. ICCAD 2004: 246-253
40		Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Modeling unbuffered latches for timing analysis. ICCAD 2004: 254-260
39		Maged Ghoneima, Yehea I. Ismail: Formal derivation of optimal active shielding for low-power on-chip buses. ICCAD 2004: 800-807
38		Maged Ghoneima, Yehea I. Ismail: Low power coupling-based encoding for on-chip buses. ISCAS (2) 2004: 325-328
37		Maged Ghoneima, Yehea I. Ismail: Effect of relative delay on the dissipated energy in coupled interconnects. ISCAS (2) 2004: 525-528
36		Daniel Dai, Yehea I. Ismail, Wei Wang, Hanif M. Ladak: Powder-based fabrication techniques for single-wall carbon nanotube circuits. ISCAS (3) 2004: 701-704
35		Maged Ghoneima, Yehea I. Ismail: Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. ISLPED 2004: 66-69
34		Masud H. Chowdhury, Yehea I. Ismail: Possible Noise Failure Modes in Static and Dynamic Circuits. IWSOC 2004: 123-126
33		Maged Ghoneima, Yehea I. Ismail: Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses. IEEE Trans. VLSI Syst. 12(12): 1348-1359 (2004)
32		Shizhong Mei, Yehea I. Ismail: Modeling skin and proximity effects with reduced realizable RL circuits. IEEE Trans. VLSI Syst. 12(4): 437-447 (2004)
31		Yehea I. Ismail, Chirayu S. Amin: Computation of signal-threshold crossing times directly from higher order moments. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1264-1276 (2004)
	2003
30		Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail: Realizable RLCK circuit crunching. DAC 2003: 226-231
29		Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail: Efficient model order reduction including skin effect. DAC 2003: 232-237
28		Maged Ghoneima, Yehea I. Ismail: Optimum positioning of interleaved repeaters In bidirectional buses. DAC 2003: 586-591
27		Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Weibull Based Analytical Waveform Model. ICCAD 2003: 161-168
26		Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter: Realizable reduction of RLC circuits using node elimination. ISCAS (3) 2003: 494-497
25		Shizhong Mei, Yehea I. Ismail: Modeling skin effect with reduced decoupled R-L circuits. ISCAS (4) 2003: 588-591
24		Noha H. Mahmoud, Yehea I. Ismail: Accurate rise time and overshoots estimation in RLC interconnects. ISCAS (5) 2003: 477-480
23		Masud H. Chowdhury, Yehea I. Ismail: Analysis of Coupling Noise in Dynamic Circuit. IWSOC 2003: 320-325
22		Yehea I. Ismail: Improved model-order reduction by using spacial information in moments. IEEE Trans. VLSI Syst. 11(5): 900-908 (2003)
21		Yehea I. Ismail, Eby G. Friedman: On the Extraction of On-Chip Inductance. Journal of Circuits, Systems, and Computers 12(1): 31-40 (2003)
	2002
20		Yehea I. Ismail: Efficient model order reduction via multi-node moment matching. ICCAD 2002: 767-774
19		Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter: Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. ISCAS (4) 2002: 197-200
18		Yehea I. Ismail: Evaluating noise pulses in RC networks due to capacitive coupling. ISCAS (5) 2002: 653-656
17		Yehea I. Ismail, Byron Krauter: Guest editorial: special issue on on-chip inductance in high-speed integrated circuits. IEEE Trans. VLSI Syst. 10(6): 683-684 (2002)
16		Yehea I. Ismail: On-chip inductance cons and pros. IEEE Trans. VLSI Syst. 10(6): 685-694 (2002)
15		Yehea I. Ismail, Eby G. Friedman: DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 131-144 (2002)
14		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Inductance Effects in RLC Trees. Journal of Circuits, Systems, and Computers 11(3): 305- (2002)
	2001
13		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Exploiting the on-chip inductance in high-speed clock distribution networks. IEEE Trans. VLSI Syst. 9(6): 963-973 (2001)
	2000
12		Yehea I. Ismail, Eby G. Friedman: Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans. VLSI Syst. 8(2): 195-206 (2000)
11		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Equivalent Elmore delay for RLC trees. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 83-97 (2000)
	1999
10		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Equivalent Elmore Delay for RLC Trees. DAC 1999: 715-720
9		Yehea I. Ismail, Eby G. Friedman: Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. DAC 1999: 721-724
8		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Inductance Effects in RLC Trees. Great Lakes Symposium on VLSI 1999: 56-59
7		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Repeater insertion in tree structured inductive interconnect. ICCAD 1999: 420-424
6		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Signal waveform characterization in RLC trees. ISCAS (6) 1999: 190-193
5		Yehea I. Ismail, Eby G. Friedman: Repeater insertion in RLC lines for minimum propagation delay. ISCAS (6) 1999: 404-407
4		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Figures of merit to characterize the importance of on-chip inductance. IEEE Trans. VLSI Syst. 7(4): 442-449 (1999)
	1998
3		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Figures of Merit to Characterize the Importance of On-Chip Inductance. DAC 1998: 560-565
2		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. Great Lakes Symposium on VLSI 1998: 39-44
1		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Power dissipated by CMOS gates driving lossless transmission lines. ISLPED 1998: 139-142

Coauthor Index

1	Chirayu S. Amin	[26] [27] [29] [30] [31] [40] [41] [42] [44] [49] [52] [53]
2	Javed Barkatullah	[48]
3	Keith A. Bowman	[59]
4	Umakanta Choudhury	[53]
5	Masud H. Chowdhury	[19] [23] [26] [30] [34] [44] [51] [57]
6	Daniel Dai	[36]
7	Florentin Dartu	[27] [40] [42] [49] [52] [53]
8	Debasish Das	[62] [83]
9	Ali Dasdan	[65] [81]
10	V. K. De	[85]
11	Vivek De	[47] [50] [56] [58] [59] [60] [86]
12	Eby G. Friedman	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [21]
13	Maged Ghoneima	[28] [33] [35] [37] [38] [39] [43] [46] [47] [48] [50] [54] [56] [58] [59] [60]
14	Nagib Hakim	[53]
15	Frank Huebbers	[65] [74] [81]
16	Russ Joseph	[74]
17	Tanay Karnik	[85] [86]
18	Chandramouli V. Kashyap	[19] [26]
19	D. E. Khalil	[85]
20	DiaaEldin Khalil	[61] [63] [76] [86] [90]
21	Muhammad M. Khellah	[47] [48] [50] [56] [58] [59] [60] [85] [86]
22	Kip Killpack	[53] [62] [83]
23	Nam-Sung Kim	[85]
24	Sami Kirolos	[88] [89]
25	Byron Krauter	[17] [19] [26]
26	Ja Chun Ku	[45] [66] [67] [70] [71] [72] [73] [75] [77] [78] [80] [84]
27	Nasser Kurd	[48]
28	John Lach	[55]
29	Hanif M. Ladak	[36]
30	Jieyi Long	[80]
31	Noha H. Mahmoud	[24] [54]
32	Arindam Mallik	[51] [73]
33	Yehia Massoud	[88] [89]
34	Shizhong Mei	[25] [29] [32] [69]
35	Gokhan Memik	[45] [51] [67] [72] [73]
36	Seda Ogrenci Memik (Seda Ogrenci)	[80]
37	Noel Menezes	[53]
38	Ke Meng	[74]
39	José Luis Neves	[1] [2] [3] [4] [6] [7] [8] [10] [11] [13] [14]
40	Srikanth Nimmagadda	[48]
41	Serkan Ozdemir	[45] [67] [72] [73]
42	Dusan Petranovic	[64] [82]
43	Gang Qu	[55] [68]
44	Ahmed Shebaita	[62] [64] [79] [82] [83]
45	Ahmed M. Shebaita	[49]
46	Debjit Sinha	[63]
47	James Tschanz	[47] [48] [50] [56] [59]
48	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[68]
49	Wei Wang	[36]
50	Yibin Ye	[47] [48]
51	Hai Zhou	[62] [63] [68] [83]

Colors in the list of coauthors