 | 2008 |
|---|
| 7 |       | A. Neslin Ismailoglu,
Murat Askar:
SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation.
DSD 2008: 566-571 |
| 2007 |
|---|
| 6 | | A. Neslin Ismailoglu,
Murat Askar:
Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders.
ISCAS 2007: 3259-3262 |
| 2006 |
|---|
| 5 | | A. Neslin Ismailoglu,
O. Benderli,
Soner Yesil,
Refik Sever,
Burak Okcan,
O. Sengul,
Rusen Öktem:
GEZGIN & GEZGIN-2: Adaptive Real-Time Image Processing Subsystems for Earth Observing Small Satellites.
AHS 2006: 351-358 |
| 2004 |
|---|
| 4 | | Refik Sever,
A. Neslin Ismailoglu,
Yusuf Çagatay Tekmen,
Murat Askar,
Burak Okcan:
A High Speed FPGA Implementation of the Rijndael Algorithm.
DSD 2004: 358-362 |
| 3 |  | Refik Sever,
A. Neslin Ismailoglu,
Yusuf Çagatay Tekmen,
Murat Askar:
A high speed ASIC implementation of the Rijndael algorithm.
ISCAS (2) 2004: 541-544 |
| 2 | | Soner Yesil,
A. Neslin Ismailoglu,
Yusuf Çagatay Tekmen,
Murat Askar:
Two fast RSA implementations using high-radix montgomery algorithm.
ISCAS (2) 2004: 557-560 |
| 2003 |
|---|
| 1 | | O. Benderli,
Yusuf Çagatay Tekmen,
A. Neslin Ismailoglu:
A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications.
DSD 2003: 384-391 |
