 | 2007 |
|---|
| 11 |       | Tuomas Järvinen,
Perttu Salmela,
Harri Sorokin,
Jarmo Takala:
Stride Permutation Networks for Array Processors.
VLSI Signal Processing 49(1): 51-71 (2007) |
| 2006 |
|---|
| 10 | | Tuomas Järvinen,
Perttu Salmela,
Konsta Punkka,
Jarmo Takala:
Evaluation of stride permutation networks.
ISCAS 2006 |
| 9 | | Perttu Salmela,
Pekka Jääskeläinen,
Tuomas Järvinen,
Jarmo Takala:
Software Pipelining Support for Transport Triggered Architecture Processors.
SAMOS 2006: 237-247 |
| 2005 |
|---|
| 8 | | Perttu Salmela,
Tuomas Järvinen,
Teemu Sipilä,
Jarmo Takala:
256-State Rate 1/2 Viterbi Decoder on TTA Processor.
ASAP 2005: 370-378 |
| 7 | | Tuomas Järvinen,
Perttu Salmela,
Teemu Sipilä,
Jarmo Takala:
Systematic approach for path metric access in Viterbi decoders.
IEEE Transactions on Communications 53(5): 755-759 (2005) |
| 2004 |
|---|
| 6 | | Tuomas Järvinen,
Perttu Salmela,
Harri Sorokin,
Jarmo Takala:
Stride Permutation Networks for Array Processors.
ASAP 2004: 376-386 |
| 5 | | Tuomas Järvinen,
Jarmo Takala:
Register-Based Permutation Networks for Stride Permutations.
SAMOS 2004: 108-117 |
| 2003 |
|---|
| 4 | | Jarmo Takala,
Tuomas Järvinen,
Harri Sorokin:
Conflict-free parallel memory access scheme for FFT processors.
ISCAS (4) 2003: 524-527 |
| 3 |  | Tuomas Järvinen,
Perttu Salmela,
Teemu Sipilä,
Jarmo Takala:
In-Place Storage of Path Metrics in Viterbi Decoders.
VLSI-SOC 2003: 295-300 |
| 2002 |
|---|
| 2 | | Jarmo Takala,
Tuomas Järvinen,
Jari Nikara:
Register-based reordering networks for matrix transpose.
ISCAS (4) 2002: 874-877 |
| 2001 |
|---|
| 1 | | Tuomas Järvinen,
Jarmo Takala,
David Akopian,
Jukka Saarinen:
Register-based multi-port perfect shuffle networks.
ISCAS (4) 2001: 306-309 |
