 | 2009 |
| 17 |  | Atif Raza Jafri,
Daoud Karakolah,
Amer Baghdadi,
Michel Jézéquel:
ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications.
DATE 2009: 1620-1625 |
| 16 |  | Camille Leroux,
Christophe Jégo,
Patrick Adde,
Michel Jézéquel:
High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping.
Signal Processing Systems 57(3): 349-361 (2009) |
| 2008 |
| 15 |  | Hazem Moussa,
Amer Baghdadi,
Michel Jézéquel:
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder.
DAC 2008: 429-434 |
| 14 |  | Hazem Moussa,
Amer Baghdadi,
Michel Jézéquel:
Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder.
ISCAS 2008: 97-100 |
| 13 |  | Camille Leroux,
Christophe Jégo,
Patrick Adde,
Michel Jézéquel,
Deepak Gupta:
A highly parallel Turbo Product Code decoder without interleaving resource.
SiPS 2008: 1-6 |
| 2007 |
| 12 |  | Hazem Moussa,
Olivier Muller,
Amer Baghdadi,
Michel Jézéquel:
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding.
DATE 2007: 654-659 |
| 11 |  | Camille Leroux,
Christophe Jégo,
Patrick Adde,
Michel Jézéquel:
Towards Gb/s turbo decoding of product code onto an FPGA device.
ISCAS 2007: 909-912 |
| 10 |  | Haisheng Liu,
Jean-Philippe Diguet,
Christophe Jégo,
Michel Jézéquel,
Emmanuel Boutillon:
Energy Efficient Turbo Decoder with Reduced State Metric Quantization.
SiPS 2007: 237-242 |
| 2006 |
| 9 |  | Olivier Muller,
Amer Baghdadi,
Michel Jézéquel:
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.
DATE 2006: 1330-1335 |
| 8 |  | Olivier Muller,
Amer Baghdadi,
Michel Jézéquel:
On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference.
GLOBECOM 2006 |
| 7 |  | Erwan Piriou,
Christophe Jégo,
Patrick Adde,
Raphaël Le Bidan,
Michel Jézéquel:
Efficient architecture for Reed Solomon block turbo code.
ISCAS 2006 |
| 6 |  | Matthieu Arzel,
Fabrice Seguin,
Cyril Lahuec,
Michel Jézéquel:
Semi-iterative analog turbo decoding.
ISCAS 2006 |
| 5 |  | Erwan Piriou,
Christophe Jégo,
Patrick Adde,
Michel Jézéquel:
A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes.
ISVLSI 2006: 430-431 |
| 4 |  | Erwan Piriou,
Christophe Jégo,
Patrick Adde,
Michel Jézéquel:
Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding.
ReCoSoC 2006: 152-159 |
| 2005 |
| 3 |  | Matthieu Arzel,
Cyril Lahuec,
Fabrice Seguin,
David Gnaedig,
Michel Jézéquel:
. Analog slice turbo decoding.
ISCAS (1) 2005: 332-335 |
| 2 |  | Ramesh Pyndiah,
Michel Jézéquel:
Foreword / Éditorial.
Annales des Télécommunications 60(1-2): 6-9 (2005) |
| 1 |  | David Gnaedig,
Emmanuel Boutillon,
Michel Jézéquel,
Vincent C. Gaudet,
P. Glenn Gulak:
On Multiple Slice Turbo Codes.
Annales des Télécommunications 60(1-2): 79-102 (2005) |