| 2009 | ||
|---|---|---|
| 38 | Bruce L. Jacob: The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It Morgan & Claypool Publishers 2009 | |
| 37 | Cagdas Dirik, Bruce L. Jacob: The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization. ISCA 2009: 279-289 | |
| 2008 | ||
| 36 | Bruce L. Jacob, Spencer W. Ng, David T. Wang: Memory Systems: Cache, DRAM, Disk Morgan Kaufmann 2008 | |
| 35 | Ankush Varma, Eric Debes, Igor Kozintsev, Paul Klein, Bruce L. Jacob: Accurate and fast system-level power modeling: An XScale-based case study. ACM Trans. Embedded Comput. Syst. 7(3): (2008) | |
| 2007 | ||
| 34 | Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. Jacob: Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling. HPCA 2007: 109-120 | |
| 33 | Ankush Varma, Bruce L. Jacob, Eric Debes, Igor Kozintsev, Paul Klein: Accurate and fast system-level power modeling: An XScale-based case study. ACM Trans. Embedded Comput. Syst. 6(4): (2007) | |
| 2006 | ||
| 32 | Ankush Varma, Muhammad Yaqub Afridi, Akin Akturk, Paul Klein, Allen R. Hefner, Bruce L. Jacob: Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study. CASES 2006: 54-64 | |
| 31 | Aamer Jaleel, Matthew Mattina, Bruce L. Jacob: Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads. HPCA 2006: 88-98 | |
| 30 | Samuel Rodríguez, Bruce L. Jacob: Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm). ISLPED 2006: 25-30 | |
| 29 | Aamer Jaleel, Bruce L. Jacob: In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs). IEEE Trans. Computers 55(5): 559-574 (2006) | |
| 2005 | ||
| 28 | Hongxia Wang, Samuel Rodríguez, Cagdas Dirik, Amol Gole, Vincent Chan, Bruce L. Jacob: TERPS: the embedded reliable processing system. ASP-DAC 2005: 1-2 | |
| 27 | Aamer Jaleel, Bruce L. Jacob: Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions. HPCA 2005: 191-200 | |
| 26 | Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Manoj Franklin, Bruce L. Jacob, Chau-Wen Tseng, Donald Yeung: BioBench: A Benchmark Suite of Bioinformatics Applications. ISPASS 2005: 2-9 | |
| 25 | Justin Teller, Charles B. Silio Jr., Bruce L. Jacob: Performance characteristics of MAUI: an intelligent memory system architecture. Memory System Performance 2005: 44-53 | |
| 24 | David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Kathleen Baynes, Aamer Jaleel, Bruce L. Jacob: DRAMsim: a memory system simulator. SIGARCH Computer Architecture News 33(4): 100-107 (2005) | |
| 2004 | ||
| 23 | Bharath Iyer, Sadagopan Srinivasan, Bruce L. Jacob: Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs. ISCA 2004: 364-375 | |
| 2003 | ||
| 22 | Ankush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury, Lakshmi Srinivasan, Bruce L. Jacob: A control-theoretic approach to dynamic voltage scheduling. CASES 2003: 255-266 | |
| 21 | Paul Kohout, Brinda Ganesh, Bruce L. Jacob: Hardware support for real-time operating systems. CODES+ISSS 2003: 45-51 | |
| 20 | Bruce L. Jacob, Shuvra S. Bhattacharyya: Introduction to the two special issues on memory. ACM Trans. Embedded Comput. Syst. 2(1): 1-4 (2003) | |
| 19 | Bruce L. Jacob: A Case for Studying DRAM Issues at the System Level. IEEE Micro 23(4): 44-56 (2003) | |
| 18 | Kathleen Baynes, Chris Collins, Eric Fiterman, Brinda Ganesh, Paul Kohout, Christine Smit, Tiebing Zhang, Bruce L. Jacob: The Performance and Energy Consumption of Embedded Real-Time Operating Systems. IEEE Trans. Computers 52(11): 1454-1469 (2003) | |
| 2002 | ||
| 17 | Bruce L. Jacob, Shuvra S. Bhattacharyya: Introduction to the two special issues on memory. ACM Trans. Embedded Comput. Syst. 1(1): 2-5 (2002) | |
| 2001 | ||
| 16 | Kathleen Baynes, Chris Collins, Eric Fiterman, Brinda Ganesh, Paul Kohout, Christine Smit, Tiebing Zhang, Bruce L. Jacob: The performance and energy consumption of three embedded real-time operating systems. CASES 2001: 203-210 | |
| 15 | Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob: Transparent data-memory organizations for digital signal processors. CASES 2001: 44-48 | |
| 14 | Aamer Jaleel, Bruce L. Jacob: Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers. HiPC 2001: 282-293 | |
| 13 | Aamer Jaleel, Bruce L. Jacob: In-Line Interrupt Handling for Software-Managed TLBs. ICCD 2001: 62-67 | |
| 12 | Vinodh Cuppu, Bruce L. Jacob: Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?. ISCA 2001: 62-71 | |
| 11 | Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge: High-Performance DRAMs in Workstation Environments. IEEE Trans. Computers 50(11): 1133-1153 (2001) | |
| 10 | Bruce L. Jacob, Trevor N. Mudge: Uniprocessor Virtual Memory without TLBs. IEEE Trans. Computers 50(5): 482-499 (2001) | |
| 2000 | ||
| 9 | Brian Davis, Bruce L. Jacob, Trevor N. Mudge: The New DRAM Interfaces: SDRAM, RDRAM and Variants. ISHPC 2000: 26-31 | |
| 1999 | ||
| 8 | David R. Kaeli, Bruce L. Jacob: Fifth Annual Workshop on Computer Education. HPCA 1999: 320 | |
| 7 | Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge: A Performance Comparison of Contemporary DRAM Architectures. ISCA 1999: 222-233 | |
| 1998 | ||
| 6 | Bruce L. Jacob, Trevor N. Mudge: A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations. ASPLOS 1998: 295-306 | |
| 5 | Bruce L. Jacob, Trevor N. Mudge: Virtual Memory: Issues of Implementation. IEEE Computer 31(6): 33-43 (1998) | |
| 1997 | ||
| 4 | Bruce L. Jacob, Trevor N. Mudge: Software-Managed Address Translation. HPCA 1997: 156-167 | |
| 3 | Bruce L. Jacob, Peter M. Chen, Seth R. Silverman, Trevor N. Mudge: A Comment on ``An Analytical Model for Designing Memory Hierarchies''. IEEE Trans. Computers 46(10): 1151 (1997) | |
| 1996 | ||
| 2 | Bruce L. Jacob, Trevor N. Mudge: The trading function in action. ACM SIGOPS European Workshop 1996: 241-247 | |
| 1 | Bruce L. Jacob, Peter M. Chen, Seth R. Silverman, Trevor N. Mudge: An Analytical Model for Designing Memory Hierarchies. IEEE Trans. Computers 45(10): 1180-1194 (1996) | |