 | 2007 |
|---|
| 10 |       | Jason Cong,
Guoling Han,
Ashok Jagannathan,
Glenn Reinman,
Krzysztof Rutkowski:
Accelerating Sequential Applications on CMPs Using Core Spilling.
IEEE Trans. Parallel Distrib. Syst. 18(8): 1094-1107 (2007) |
| 2006 |
|---|
| 9 | | Jason Cong,
Ashok Jagannathan,
Yuchun Ma,
Glenn Reinman,
Jie Wei,
Yan Zhang:
An automated design flow for 3D microarchitecture evaluation.
ASP-DAC 2006: 384-389 |
| 2005 |
|---|
| 8 | | Ashok Jagannathan,
Hannah Honghua Yang,
Kris Konigsfeld,
Dan Milliron,
Mosur Mohan,
Michail Romesis,
Glenn Reinman,
Jason Cong:
Microarchitecture evaluation with floorplanning and interconnect pipelining.
ASP-DAC 2005: 8-15 |
| 7 | | Jason Cong,
Yiping Fan,
Guoling Han,
Ashok Jagannathan,
Glenn Reinman,
Zhiru Zhang:
Instruction set extension with shadow registers for configurable processors.
FPGA 2005: 99-106 |
| 6 | | Jason Cong,
Ashok Jagannathan,
Glenn Reinman,
Yuval Tamir:
Understanding the energy efficiency of SMT and CMP with multiclustering.
ISLPED 2005: 48-53 |
| 2003 |
|---|
| 5 | | Jason Cong,
Ashok Jagannathan,
Glenn Reinman,
Michail Romesis:
Microarchitecture evaluation with physical planning.
DAC 2003: 32-35 |
| 2002 |
|---|
| 4 | | Ashok Jagannathan,
Sung-Woo Hur,
John Lillis:
A fast algorithm for context-aware buffer insertion.
ACM Trans. Design Autom. Electr. Syst. 7(1): 173-188 (2002) |
| 2000 |
|---|
| 3 | | Ashok Jagannathan,
Sung-Woo Hur,
John Lillis:
A fast algorithm for context-aware buffer insertion.
DAC 2000: 368-373 |
| 2 | | Sung-Woo Hur,
Ashok Jagannathan,
John Lillis:
Timing-driven maze routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 234-241 (2000) |
| 1999 |
|---|
| 1 | | Sung-Woo Hur,
Ashok Jagannathan,
John Lillis:
Timing driven maze routing.
ISPD 1999: 208-213 |
