 | 2009 |
|---|
| 10 |       | Ali Jahanian,
Morteza Saheb Zamani:
Improved performance and yield with chip master planning design methodology.
ACM Great Lakes Symposium on VLSI 2009: 185-190 |
| 9 | | Naser MohammadZadeh,
Minoo Mirsaeedi,
Ali Jahanian,
Morteza Saheb Zamani:
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network.
DATE 2009: 833-838 |
| 2008 |
|---|
| 8 | | Ali Jahanian,
Morteza Saheb Zamani:
Performance and Timing Yield Enhancement using Highway-on-Chip Planning.
DSD 2008: 165-172 |
| 7 | | Adel Dokhanchi,
Mostafa Rezvani,
Ali Jahanian,
Morteza Saheb Zamani:
Performance Improvement of Physical Retiming with Shortcut Insertion.
ISVLSI 2008: 215-220 |
| 2007 |
|---|
| 6 | | Ali Jahanian,
Morteza Saheb Zamani:
Improved timing closure by early buffer planning in floor-placement design flow.
ACM Great Lakes Symposium on VLSI 2007: 558-563 |
| 5 | | Mehdi Saeedi,
Morteza Saheb Zamani,
Ali Jahanian:
Evaluation, prediction and reduction of routing congestion.
Microelectronics Journal 38(8-9): 942-958 (2007) |
| 2006 |
|---|
| 4 | | Mehdi Saeedi,
Morteza Saheb Zamani,
Ali Jahanian:
Prediction and reduction of routing congestion.
ISPD 2006: 72-77 |
| 3 | | Ali Jahanian,
Morteza Saheb Zamani:
Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits.
ISVLSI 2006: 411-415 |
| 2005 |
|---|
| 2 | | Hamid Safizadeh,
Hamid Noori,
Mehdi Sedighi,
Ali Jahanian,
Neda Zolfaghari:
Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms.
DSD 2005: 227-230 |
| 2004 |
|---|
| 1 | | Mohammad K. Akbari,
Ali Jahanian,
Mohsen Naderi,
Bahman Javadi:
Area Efficient, Low Power and Robust Design for Add-Compare-Select Units.
DSD 2004: 611-614 |
