 | 2009 |
|---|
| 5 |       | Javier Hormigo,
Manuel Ortiz,
Francisco J. Quiles,
Francisco J. Jaime,
Julio Villalba,
Emilio L. Zapata:
Efficient Implementation of Carry-Save Adders in FPGAs.
ASAP 2009: 207-210 |
| 2008 |
|---|
| 4 | | Francisco J. Jaime,
Javier Hormigo,
Julio Villalba,
Emilio L. Zapata:
SIMD Enhancements for a Hough Transform Implementation.
DSD 2008: 899-903 |
| 3 | | Francisco J. Jaime,
Javier Hormigo,
Julio Villalba,
Emilio L. Zapata:
New SIMD instructions set for image processing applications enhancement.
ICIP 2008: 1396-1399 |
| 2 | | Francisco J. Jaime,
Julio Villalba,
Javier Hormigo,
Emilio L. Zapata:
Pipelined Architecture for Additive Range Reduction.
Signal Processing Systems 53(1-2): 103-112 (2008) |
| 2006 |
|---|
| 1 | | Francisco J. Jaime,
Julio Villalba,
Javier Hormigo,
Emilio L. Zapata:
Pipelined Range Reduction for Floating Point Numbers.
ASAP 2006: 145-152 |
