 | 2009 |
|---|
| 8 |       | Luke Terry,
Vladimir Roitch,
Shoeb Tufail,
Kirit Singh,
Omair Taraq,
Wayne Luk,
Peter Jamieson:
Harnessing Human Computation Cycles for the FPGA Placement Problem.
ERSA 2009: 188-194 |
| 7 |  | Jason Luu,
Ian Kuon,
Peter Jamieson,
Ted Campbell,
Andy Ye,
Wei Mark Fang,
Jonathan Rose:
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.
FPGA 2009: 133-142 |
| 2008 |
|---|
| 6 | | Tobias Becker,
Peter Jamieson,
Wayne Luk,
Peter Y. K. Cheung,
Tero Rissa:
Towards benchmarking energy efficiency of reconfigurable architectures.
FPL 2008: 691-694 |
| 2005 |
|---|
| 5 | | Peter Jamieson,
Jonathan Rose:
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs.
FPL 2005: 305-310 |
| 2003 |
|---|
| 4 | | Angelos Bilas,
Courtney R. Gibson,
Reza Azimi,
Rosalia Christodoulopoulou,
Peter Jamieson:
Using System Emulation to Model Next-Generation Shared Virtual Memory Clusters.
Cluster Computing 6(4): 325-338 (2003) |
| 2002 |
|---|
| 3 | | Peter Jamieson,
Angelos Bilas:
CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters.
HPCA 2002: 263-274 |
| 2001 |
|---|
| 2 | | Peter Jamieson,
Angelos Bilas:
CableS : Thread Control and Memory System Extensions for Shared Virtual Memory Clusters.
WOMPAT 2001: 170-184 |
| 2000 |
|---|
| 1 | | Kathy Lynch,
Angela Carbone,
Peter Jamieson,
David Arnott:
Adopting a studio-based education approach into information technology (poster session).
ACSE 2000: 254 |
