Jack S. N. Jean

	2006
19		Fei Wang, Jack S. N. Jean: Architectural Support for Runtime 2D Partial Reconfiguration. ERSA 2006: 231-236
	2005
18		Fei Wang, Jack S. N. Jean, Shuxia Sun: Aspect Ratio Effects on Reconfigurable Computing. ERSA 2005: 71-77
	2004
17		Xinzhong Guo, Jack S. N. Jean: Design Enumeration of Mapping 2D FFT onto FPGA Based Reconfigurable Computers. ERSA 2004: 305-306
	2003
16		Jack S. N. Jean, Xinzhong Guo, Fei Wang, Lei Song, Ying Zhang: A Study of Mapping Generalized Sliding Window Operations on Reconfigurable Computers. Engineering of Reconfigurable Systems and Algorithms 2003: 51-57
15		Xuejun Liang, Jack S. N. Jean: Mapping of generalized template matching onto reconfigurable computers. IEEE Trans. VLSI Syst. 11(3): 485-498 (2003)
	2001
14		Xuejun Liang, Jack S. N. Jean, Karen A. Tomko: Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems. The Journal of Supercomputing 19(1): 77-91 (2001)
	2000
13		Xuejun Liang, Jack S. N. Jean: Interface Design for the Mapping of Generalized Template Matching on Reconfigurable Systems. PDPTA 2000
12		Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko, Yan Wang: Automatic Target Recognition with Dynamic Reconfiguration. VLSI Signal Processing 25(1): 39-53 (2000)
	1999
11		Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko: Accelerating an IR Automatic Target Recognition Application with FPGAs. FCCM 1999: 290-291
10		Jack S. N. Jean, Xuejun Liang, Karen A. Tomko: Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems. PDPTA 1999: 1111-1117
9		Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook: Dynamic Reconfiguration to Support Concurrent Applications. IEEE Trans. Computers 48(6): 591-602 (1999)
8		Joseph A. Fernando, Jack S. N. Jean: Processor array design with FPGA area constraint. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 253-264 (1999)
	1998
7		Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Robert Cook, Jignesh Shah: Dynamic Reconfiguration to Support Concurrent Applications. FCCM 1998: 302-303
6		Hong K. Kim, Jack S. N. Jean: Parallel Optimistic Logic Simulation with Event Lookahead. ICPP 1998: 20-27
	1996
5		Hong K. Kim, Jack S. N. Jean: Concurrency Preserving Rartitioning (CPP) for Parallel Logic Simulation. Workshop on Parallel and Distributed Simulation 1996: 98-105
	1995
4		Joseph A. Fernando, Jack S. N. Jean: Interfacing FPGA/VLSI Processor Arrays. ASAP 1995: 230-237
	1994
3		Jin Wang, Jack S. N. Jean: Segmentation of merged characters by neural networks and shortest path. Pattern Recognition 27(5): 649-658 (1994)
	1993
2		Jin Wang, Jack S. N. Jean: Segmentation of Merged Characters by Neural Networks and Shortest-Path. SAC 1993: 762-769
1		Jin Wang, Jack S. N. Jean: Resolving multifont character confusion with neural networks. Pattern Recognition 26(1): 175-187 (1993)

Coauthor Index

1	Robert Cook	[7] [9]
2	Brian Drozd	[11] [12]
3	Joseph A. Fernando	[4] [8]
4	Xinzhong Guo	[16] [17]
5	Hong K. Kim	[5] [6]
6	Xuejun Liang	[10] [11] [12] [13] [14] [15]
7	Jignesh Shah	[7] [9]
8	Lei Song	[16]
9	Shuxia Sun	[18]
10	Karen A. Tomko	[7] [9] [10] [11] [12] [14]
11	Fei Wang	[16] [18] [19]
12	Jin Wang	[1] [2] [3]
13	Yan Wang	[12]
14	Vikram Yavagal	[7] [9]
15	Ying Zhang	[16]

Colors in the list of coauthors