Maksim Jenihhin

	2008
9		Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee: Code Coverage Analysis using High-Level Decision Diagrams. DDECS 2008: 201-206
8		Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee: Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA 2008: 222-227
7		Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz: Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD 2008: 729-734
6		Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin: Mixed hierarchical-functional fault models for targeting sequential cores. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 465-477 (2008)
	2007
5		Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski: Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS 2007: 35-40
	2006
4		Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Test Time Minimization for Hybrid BIST of Core-Based Systems. J. Comput. Sci. Technol. 21(6): 907-912 (2006)
	2004
3		Raimund Ubar, Maksim Jenihhin: Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting. DELTA 2004: 3-8
	2003
2		Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium 2003: 318-325
1		Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. DFT 2003: 225-

Coauthor Index

1	Sergei Devadze	[8]
2	Petru Eles	[1] [2] [4]
3	Peeter Ellervee	[8] [9]
4	Gert Jervan	[1] [2] [4] [8]
5	Wieslaw Kuzmicz	[7]
6	Zebo Peng	[1] [2] [4]
7	Witold A. Pleskacz	[5] [7]
8	Jaan Raik	[5] [6] [7] [8] [9]
9	Michal Rakowski	[5] [7]
10	Uljana Reinsalu	[9]
11	Raimund Ubar	[1] [2] [3] [4] [5] [6] [7] [8] [9]
12	Taavi Viilukas	[6]