Ruzica Jevtic

	2009
3		Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic: Floorplan-based FPGA interconnect power estimation in DSP circuits. SLIP 2009: 53-60
	2008
2		Ruzica Jevtic, Carlos Carreras: Analytical High-Level Power Model for LUT-Based Components. PATMOS 2008: 369-378
	2007
1		Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena: Switching Activity Models for Power Estimation in FPGA Multipliers. ARC 2007: 201-213

Coauthor Index

1	Gabriel Caffarena	[1]
2	Carlos Carreras	[1] [2] [3]
3	Vukasin Pejovic	[3]