 | 2009 |
|---|
| 9 |       | Juanjuan Chen,
Xing Wei,
Yunjian Jiang,
Qiang Zhou:
Improve clock gating through power-optimal enable function selection.
DDECS 2009: 30-33 |
| 2003 |
|---|
| 8 | | Yunjian Jiang,
Slobodan Matic,
Robert K. Brayton:
Generalized cofactoring for logic function evaluation.
DAC 2003: 155-158 |
| 7 | | Reinaldo A. Bergamaschi,
Yunjian Jiang:
State-based power analysis for systems-on-chip.
DAC 2003: 638-641 |
| 2002 |
|---|
| 6 | | Massimo Baleani,
Frank Gennari,
Yunjian Jiang,
Yatish Patel,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform.
CODES 2002: 151-156 |
| 5 | | Yunjian Jiang,
Robert K. Brayton:
Software synthesis from synchronous specifications using logic simulation techniques.
DAC 2002: 319-324 |
| 4 | | Robert K. Brayton,
M. Gao,
Jie-Hong Roland Jiang,
Yunjian Jiang,
Yinghua Li,
Alan Mishchenko,
Subarnarekha Sinha,
Tiziano Villa:
Optimization of Multi-Valued Multi-Level Networks.
ISMVL 2002: 168- |
| 3 |  | Yunjian Jiang,
Robert K. Brayton:
Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic.
IWLS 2002: 327-332 |
| 2001 |
|---|
| 2 | | Yunjian Jiang,
Robert K. Brayton:
Logic optimization and code generation for embedded control applications.
CODES 2001: 225-229 |
| 2000 |
|---|
| 1 | | Yunjian Jiang,
Robert K. Brayton:
Don't Cares and Multi-Valued Logic Network Minimization.
ICCAD 2000: 520-525 |
