 | 2009 |
|---|
| 10 |       | Jesús Lázaro,
Armando Astarloa,
Unai Bidarte,
Jaime Jimenez,
Aitzol Zuloaga:
AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications.
ARC 2009: 312-317 |
| 9 | | Armando Astarloa,
Jesús Lázaro,
Unai Bidarte,
Aitzol Zuloaga,
Jaime Jimenez:
DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus.
ICDCS Workshops 2009: 472-475 |
| 2008 |
|---|
| 8 | | Armando Astarloa,
Unai Bidarte,
Jaime Jimenez,
Jesús Lázaro,
Iñigo Martínez de Alegría:
Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes.
ATC 2008: 603-614 |
| 2007 |
|---|
| 7 | | Jagoba Arias,
Jesús Lázaro,
Aitzol Zuloaga,
Jaime Jimenez,
Armando Astarloa:
GPS-less location algorithm for wireless sensor networks.
Computer Communications 30(14-15): 2904-2916 (2007) |
| 6 | | Armando Astarloa,
Aitzol Zuloaga,
Unai Bidarte,
José Luis Martín,
Jesús Lázaro,
Jaime Jimenez:
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs.
Journal of Systems Architecture 53(9): 629-643 (2007) |
| 2006 |
|---|
| 5 | | Jagoba Arias,
Eduardo Santos,
Itziar Marín,
Jaime Jimenez,
Jesús Lázaro,
Aitzol Zuloaga:
Node Synchronization in Wireless Sensor Networks.
ICWMC 2006: 50 |
| 4 | | Jaime Jimenez,
Iker Hoyos,
Jagoba Arias,
Armando Astorlao,
José Luis Martín:
Modifying Slots in Test Vectors to Validate Decoders of a Train Network.
ICWMC 2006: 58 |
| 3 | | Jaime Jimenez,
José Luis Martín,
Aitzol Zuloaga,
Unai Bidarte,
Jagoba Arias:
Comparison of two designs for the multifunction vehicle bus.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 797-805 (2006) |
| 2004 |
|---|
| 2 |  | Jagoba Arias,
Jesús Lázaro,
Aitzol Zuloaga,
Jaime Jimenez:
Doppler Location Algorithm for Wireless Sensor Networks.
International Conference on Wireless Networks 2004: 509-514 |
| 2003 |
|---|
| 1 | | Unai Bidarte,
Armando Astarloa,
Aitzol Zuloaga,
Jaime Jimenez,
Iñigo Martínez de Alegría:
Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements.
FPL 2003: 497-506 |
