Peer Johannsen

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2001

2 Peer Johannsen: BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction. CAV 2001: 373-377

1 Peer Johannsen, Rolf Drechsler: Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. VLSI-SOC 2001: 361-374

	2001
2		Peer Johannsen: BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction. CAV 2001: 373-377
1		Peer Johannsen, Rolf Drechsler: Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. VLSI-SOC 2001: 361-374

Coauthor Index

1 Rolf Drechsler [1]