Rajiv V. Joshi

	2009
40		Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, W. Reohr, Sani R. Nassif, Kevin J. Nowka: Statistical yield analysis of silicon-on-insulator embedded DRAM. ISQED 2009: 190-194
39		Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi: The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED 2009: 607-612
	2008
38		Rouwaida Kanj, Rajiv V. Joshi, Zhou Li, Jente B. Kuang, Hung C. Ngo, Ying Zhou, Weiping Shi, Sani R. Nassif: SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. ISLPED 2008: 87-92
37		Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang: Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. ISQED 2008: 488-491
36		Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif: Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. ISQED 2008: 702-707
35		Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif: A Root-Finding Method for Assessing SRAM Stability. ISQED 2008: 804-809
	2007
34		Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang: A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. ISLPED 2007: 8-13
33		Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif: Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. ISQED 2007: 33-40
32		Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang: A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. VLSI Design 2007: 665-672
31		Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectronics Journal 38(8-9): 931-941 (2007)
	2006
30		Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif: Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. DAC 2006: 69-72
29		Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee: A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. DAC 2006: 977-982
28		Rajiv V. Joshi, Kaustav Banerjee, André DeHon: Tutorial 1: Emerging Technologies for VLSI Design. ISQED 2006: 4
27		Ruchir Puri, Tanay Karnik, Rajiv V. Joshi: Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. VLSI Design 2006: 5-7
	2005
26		Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, J. C. Law, Rajiv V. Joshi: A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. ICCD 2005: 574-584
25		Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi: Design of sub-90nm Circuits and Design Methodologies. ISQED 2005: 3-4
24		Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415
23		Rajiv V. Joshi, S. S. Kang, N. Zamdmar, A. Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez: Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. VLSI Design 2005: 697-702
	2004
22		Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004 ACM 2004
21		Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang: Nanoscale CMOS circuit leakage power reduction by double-gate device. ISLPED 2004: 102-107
20		Rajiv V. Joshi, K. Kroell, Ching-Te Chuang: A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. VLSI Design 2004: 832-
	2003
19		Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri: Design and CAD Challenges in sub-90nm CMOS Technologies. ICCAD 2003: 129-137
18		Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown: New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. ISLPED 2003: 168-171
17		Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang: Strained-si devices and circuits for low-power applications. ISLPED 2003: 180-183
16		Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim: Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. ISQED 2003: 153-158
15		Rajiv V. Joshi, Kaushik Roy: Design of Deep Sub-Micron CMOS Circuits. VLSI Design 2003: 15-16
14		E. N. Elnozahy, Rajiv V. Joshi: Preface. IBM Journal of Research and Development 47(5-6): 521-524 (2003)
13		Rajiv V. Joshi, Ching-Te Chuang, S. K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi: PD/SOI SRAM performance in presence of gate-to-body tunneling current. IEEE Trans. VLSI Syst. 11(6): 1106-1113 (2003)
12		R. Rodríguez, James H. Stathis, Barry P. Linder, Rajiv V. Joshi, Ching-Te Chuang: Influence and model of gate oxide breakdown on CMOS inverters. Microelectronics Reliability 43(9-11): 1439-1444 (2003)
	2002
11		R. Rodríguez, James H. Stathis, Barry P. Linder, S. Kowalczyk, Ching-Te Chuang, Rajiv V. Joshi, Gregory A. Northrop, Kerry Bernstein, A. J. Bhavnagarwala, Salvatore Lombardo: Analysis of the effect of the gate oxide breakdown on SRAM stability. Microelectronics Reliability 42(9-11): 1445-1448 (2002)
	2001
10		Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang: SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI 2001: 37-42
9		W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi: Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED 2001: 263-266
8		Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty: IBM's Blue Logic Design Methodology-Circuits and Physical Design. VLSI Design 2001: 11-12
7		Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann: Design Of Provably Correct Storage Arrays. VLSI Design 2001: 196-
	2000
6		Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang: "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED 2000: 203-206
5		Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang: A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design 2000: 44-49
	1999
4		Rajiv V. Joshi, Wei Hwang: Design Considerations and Implementation of a High Performance Dynamic Register File. VLSI Design 1999: 526-531
	1998
3		Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Ben Parker, T. V. Rajeevakumar, Kevin G. Stawiasz: Designing a Testable System on a Chip. VTS 1998: 2-7
	1997
2		W. K. Luk, Y. Katayama, Wei Hwang, Matthew R. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi: Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285
1		Wei Hwang, Rajiv V. Joshi, Walter H. Henkels: A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. ICCD 1997: 712-717

Coauthor Index

1	Dhruva Acharyya	[33]
2	Kanak Agarwal	[39]
3	Sameh W. Asaad	[3]
4	Fari Assaderaghi	[13]
5	Kaustav Banerjee	[28] [29]
6	S. Basavaiah	[3]
7	Kerry Bernstein	[11] [19]
8	A. J. Bhavnagarwala	[11]
9	Arthur A. Bright	[3]
10	Richard B. Brown	[18]
11	W. Chen	[9]
12	Kiyoung Choi	[22]
13	Ching-Te Chuang	[5] [6] [10] [11] [12] [13] [16] [17] [18] [19] [20] [21] [23] [24] [31] [32] [34] [37]
14	Peter W. Cook	[18]
15	Hamed F. Dadgour	[29]
16	Koushik K. Das	[18] [21]
17	André DeHon	[28]
18	Anirudh Devgan	[25]
19	B. El-Kareh	[2]
20	E. N. Elnozahy (Elmootazbellah (Mootaz) Elnozahy)	[14]
21	S. K. H. Fung	[13]
22	George Gristede	[9]
23	Seetharam Gundurao	[8]
24	Ruud A. Haring	[3]
25	Bob Havreluk	[3]
26	David F. Heidel	[3]
27	Walter H. Henkels	[1]
28	Wei Hwang	[1] [2] [4] [5] [6] [7] [9] [10]
29	Michael Immediato	[3]
30	Keith A. Jenkins	[3]
31	Ruchira Kamdar	[8]
32	S. S. Kang	[23]
33	Rouwaida Kanj	[30] [33] [34] [35] [36] [38] [39] [40]
34	Tanay Karnik	[25] [27]
35	Y. Katayama	[2]
36	J. Kim	[40]
37	Jae-Joon Kim	[24] [31]
38	Keunwoo Kim	[16] [17] [21] [24] [31] [32] [34] [36] [37]
39	T. Kirihata	[2]
40	Steve Klepner	[3]
41	Stephen V. Kosonocky	[3] [9]
42	S. Kowalczyk	[11]
43	K. Kroell	[20]
44	Jente B. Kuang	[26] [33] [38] [40]
45	Prabhakar Kudva	[9]
46	Andreas Kuehlmann	[7]
47	J. C. Law	[26]
48	Zhou Li	[38]
49	Zhuo Li	[35] [39]
50	Barry P. Linder	[11] [12]
51	Frank Liu	[35]
52	Shih-Hsien Lo	[24] [31]
53	Salvatore Lombardo	[11]
54	W. K. Luk	[2]
55	Chandler McDowell	[33]
56	Mesut Meterelliyoz	[40]
57	A. Mocuta	[23]
58	Saibal Mukhopadhyay	[24] [31] [37]
59	Seiji Munetoh	[2]
60	N. S. Murty	[8]
61	Sani R. Nassif	[30] [33] [35] [36] [38] [39] [40]
62	Hung C. Ngo	[26] [38]
63	Tuyet Nguyen	[33]
64	Gregory A. Northrop	[11]
65	Edward J. Nowak	[32]
66	Kevin J. Nowka	[26] [40]
67	Ben Parker	[3]
68	J. A. Pascual-Gutiérrez	[23]
69	Ruchir Puri	[16] [19] [25] [27]
70	T. V. Rajeevakumar	[3]
71	W. Reohr	[40]
72	R. Rodríguez	[11] [12]
73	Kaushik Roy	[15] [22] [24] [31]
74	Sachin Sapatnaker	[25]
75	Akashi Satoh	[2]
76	Ghavam V. Shahidi	[5] [13]
77	Melanie Sherony	[13]
78	Weiping Shi	[38] [39]
79	Jayakumaran Sivagnaname	[33]
80	James H. Stathis	[11] [12]
81	Kevin G. Stawiasz	[3]
82	Vivek Tiwari	[22]
83	Kevin W. Warren	[3]
84	Richard Williams	[36]
85	Richard Q. Williams	[32] [34]
86	S. C. Wilson	[5] [6]
87	H. Wong	[2]
88	Matthew R. Wordeman	[2]
89	P. Xiao	[2]
90	I. Yang	[13]
91	N. Zamdmar	[23]
92	Ying Zhou	[38] [39]

Colors in the list of coauthors