Horng-Fei Jyu

	1994
4		Horng-Fei Jyu, Sharad Malik: Statistical Delay Modeling in Logic Design and Synthesis. DAC 1994: 126-130
	1993
3		Horng-Fei Jyu, Sharad Malik: Statistical Timing Optimization of Combinatorial Logic Circuits. ICCD 1993: 77-80
2		Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, Kurt Keutzer: Statistical timing analysis of combinational logic circuits. IEEE Trans. VLSI Syst. 1(2): 126-137 (1993)
	1992
1		Srinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik: Statistical Timing Analysis of Combinational Circuits. ICCD 1992: 38-43

Coauthor Index

1	Srinivas Devadas	[1] [2]
2	Kurt Keutzer	[1] [2]
3	Sharad Malik	[1] [2] [3] [4]