 | 2009 |
|---|
| 10 |       | Daniel Große,
Robert Wille,
Ulrich Kühne,
Rolf Drechsler:
Contradictory antecedent debugging in bounded model checking.
ACM Great Lakes Symposium on VLSI 2009: 173-176 |
| 9 | | Ulrich Kühne,
Daniel Große,
Rolf Drechsler:
Property analysis and design understanding.
DATE 2009: 1246-1249 |
| 8 | | André Sülflow,
Görschwin Fey,
Cécile Braunstein,
Ulrich Kühne,
Rolf Drechsler:
Increasing the accuracy of SAT-based debugging.
DATE 2009: 1326-1331 |
| 2008 |
|---|
| 7 | | Daniel Große,
Ulrich Kühne,
Rolf Drechsler:
Analyzing Functional Coverage in Bounded Model Checking.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1305-1314 (2008) |
| 2007 |
|---|
| 6 | | Daniel Große,
Ulrich Kühne,
Rolf Drechsler:
Estimating functional coverage in bounded model checking.
DATE 2007: 1176-1181 |
| 5 | | Ulrich Kühne,
Daniel Große,
Rolf Drechsler:
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation.
ISVLSI 2007: 165-170 |
| 2006 |
|---|
| 4 | | Daniel Große,
Ulrich Kühne,
Rolf Drechsler:
HW/SW co-verification of embedded systems using bounded model checking.
ACM Great Lakes Symposium on VLSI 2006: 43-48 |
| 3 | | Ulrich Kühne,
Nicole Drechsler:
Finding Compact BDDs Using Genetic Programming.
EvoWorkshops 2006: 308-319 |
| 2005 |
|---|
| 2 |  | Daniel Große,
Ulrich Kühne,
Rolf Drechsler:
Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors.
GI Jahrestagung (1) 2005: 308-312 |
| 1 | | Daniel Große,
Ulrich Kühne,
Rolf Drechsler:
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking.
MTV 2005: 133-137 |
