Koji Kai

	2000
3		Koji Inoue, Koji Kai, Kazuaki Murakami: Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. Intelligent Memory Systems 2000: 169-178
	1999
2		Koji Inoue, Koji Kai, Kazuaki Murakami: Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. HPCA 1999: 218-222
	1998
1		Taku Ohsawa, Koji Kai, Kazuaki Murakami: Optimizing the DRAM refresh count for merged DRAM/logic LSIs. ISLPED 1998: 82-87

Coauthor Index

1	Koji Inoue	[2] [3]
2	Kazuaki Murakami	[1] [2] [3]
3	Taku Ohsawa	[1]