Toshiki Kanamoto

	2009
11		Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato: Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Transactions 92-A(4): 990-997 (2009)
	2008
10		Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto: Impact of Well Edge Proximity Effect on Timing. IEICE Transactions 91-A(12): 3461-3464 (2008)
9		Keiichi Suemitsu, Toshiaki Ito, Toshiki Kanamoto, Masayuki Terai, Satoshi Kotani, Shigeo Sawada: A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults. IEICE Transactions 91-A(12): 3524-3530 (2008)
	2007
8		Masahiko Omura, Toshiki Kanamoto, Michiko Tsukamoto, Mitsutoshi Shirota, Takashi Nakajima, Masayuki Terai: A Fast Characterizing Method for Large Embedded Memory Modules on SoC. IEICE Transactions 90-A(4): 815-822 (2007)
	2006
7		Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto: Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Transactions 89-A(12): 3560-3568 (2006)
6		Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto: Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation. IEICE Transactions 89-A(12): 3666-3670 (2006)
5		Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda: Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. IEICE Transactions 89-A(4): 847-855 (2006)
	2005
4		Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. ISQED 2005: 586-591
3		Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda: A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills. IEICE Transactions 88-A(11): 3180-3187 (2005)
2		Toshiki Kanamoto, Tetsuya Watanabe, Mitsutoshi Shirota, Masayuki Terai, Tatsuya Kunikiyo, Kiyoshi Ishikawa, Yoshihide Ajioka, Yasutaka Horiba: A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures. IEICE Transactions 88-A(12): 3463-3470 (2005)
1		Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills. IEICE Transactions 88-A(12): 3471-3478 (2005)

Coauthor Index

1	Yoshihide Ajioka	[2]
2	Shigekiyo Akutsu	[6]
3	Hiroyuki Amishiro	[10]
4	Wei Fong Chang	[1] [4]
5	Koutaro Hachiya	[6]
6	Masanori Hashimoto	[6] [7] [10] [11]
7	Yasutaka Horiba	[2]
8	Zhangcai Huang	[5]
9	Tetsuya Ibe	[1] [4]
10	Takahiro Ichinomiya	[6]
11	Tatsuhiko Ikeda	[7]
12	Yasuaki Inoue	[1] [3] [4] [5]
13	Hiroshi Ishikawa	[6]
14	Kiyoshi Ishikawa	[2]
15	Toshiaki Ito	[9]
16	Tetsuro Kage	[1] [4]
17	Akira Kasebe	[1] [3] [4] [5]
18	Hiroyuki Kobayashi	[6]
19	Satoshi Kotani	[9]
20	Tatsuya Kunikiyo	[2]
21	Atsushi Kurokawa	[1] [3] [4] [5] [6] [11]
22	Hiroo Masuda	[1] [3] [4] [5] [11]
23	Sakae Muromoto	[6]
24	Tamiyo Nakabayashi	[6]
25	Takashi Nakajima	[8]
26	Hidenari Nakashima	[11]
27	Keiko Natsume	[10]
28	Yasuhiro Ogasahara	[10]
29	Takaaki Okumura	[11]
30	Masahiko Omura	[8]
31	Nobuto Ono	[11]
32	Hidetoshi Onodera	[7]
33	Tsuyoshi Sakata	[11]
34	Takashi Sato	[11]
35	Shigeo Sawada	[9]
36	Mitsutoshi Shirota	[2] [8]
37	Keiichi Suemitsu	[9]
38	Hiroshi Takafuji	[11]
39	Masayuki Terai	[2] [8] [9]
40	Akira Tsuchiya	[7]
41	Michiko Tsukamoto	[8]
42	Tetsuya Watanabe	[2] [10]
43	Kenji Yamaguchi	[10]
44	Yun Yang	[5]