 | 2009 |
|---|
| 135 |       | Ji-Hye Bong,
Yong-Jin Kwon,
Kyeong-Sik Min,
Sung-Mo Kang:
New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs.
ISQED 2009: 459-464 |
| 2008 |
|---|
| 134 | | Sangho Shin,
Seokoh Yun,
Sanghyun Cho,
Jongmoon Kim,
Minseok Kang,
Wonkap Oh,
Sung-Mo Kang:
0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power.
ISCAS 2008: 1958-1961 |
| 133 | | Jae-Jin Jung,
Kwang-Hyun Baek,
Shin-Il Lim,
Suki Kim,
Sung-Mo Kang:
Design of a 6 bit 1.25 GS/s DAC for WPAN.
ISCAS 2008: 2262-2265 |
| 132 | | Yong Sin Kim,
Sung-Mo Kang:
A 8-Gb/s/pin current mode multi-level simultaneous bidirectional I/O.
ISCAS 2008: 3069-3072 |
| 131 | | Je-Hyoung Park,
Ali Shakouri,
Sung-Mo Kang:
Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages.
ISQED 2008: 600-603 |
| 2007 |
|---|
| 130 | | Andrew B. Kahng,
Sung-Mo Kang,
Wei Li,
Bao Liu:
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation.
ICCD 2007: 71-77 |
| 129 | | Yong Sin Kim,
Sung-Mo Kang:
Programmable High Speed Multi-Level Simultaneous Bidirectional I/O.
ISQED 2007: 416-419 |
| 2006 |
|---|
| 128 | | Sangho Shin,
Kwyro Lee,
Sung-Mo Kang:
2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop.
ISCAS 2006 |
| 127 | | Yong Sin Kim,
Sangho Shin,
Sung-Mo Kang:
A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration.
ISCAS 2006 |
| 126 | | Sangho Shin,
Kwyro Lee,
Sung-Mo Kang:
Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors.
ISCAS 2006 |
| 2005 |
|---|
| 125 | | Ge Yang,
Yong Sin Kim,
Sung-Mo Kang:
Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications.
ISCAS (6) 2005: 5493-5496 |
| 124 | | Ge Yang,
Seong-Ook Jung,
Kwang-Hyun Baek,
Soo Hwan Kim,
Suki Kim,
Sung-Mo Kang:
A 32-bit carry lookahead adder using dual-path all-N logic.
IEEE Trans. VLSI Syst. 13(8): 992-996 (2005) |
| 2004 |
|---|
| 123 |  | Ge Yang,
Seong-Ook Jung,
Kwang-Hyun Baek,
Soo Hwan Kim,
Suki Kim,
Sung-Mo Kang:
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic.
ISCAS (2) 2004: 781-784 |
| 122 | | Ge Yang,
Zhongda Wang,
Sung-Mo Kang:
Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates.
ISQED 2004: 421-424 |
| 121 | | Ge Yang,
Zhongda Wang,
Sung-Mo Kang:
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies.
VLSI Design 2004: 222-227 |
| 2003 |
|---|
| 120 | | Kwang-Hyun Baek,
Myung-Jun Choe,
Edward Merlo,
Sung-Mo Kang:
1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs.
ISCAS (1) 2003: 901-904 |
| 119 | | Sung-Mo Kang:
Elements of low power design for integrated systems.
ISLPED 2003: 205-210 |
| 118 | | Kwang-Hyun Baek,
Myung-Jun Choe,
Sung-Mo Kang:
An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters.
ISVLSI 2003: 80-86 |
| 117 | | Yong Sin Kim,
Soo Hwan Kim,
Kwang-Hyun Baek,
Suki Kim,
Sung-Mo Kang:
Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers.
VLSI Design 2003: 261- |
| 116 | | Ki-Wook Kim,
Seong-Ook Jung,
Taewhan Kim,
Sung-Mo Kang:
Minimum delay optimization for domino circuits - a coupling-aware approach.
ACM Trans. Design Autom. Electr. Syst. 8(2): 202-213 (2003) |
| 115 | | Chulwoo Kim,
Ki-Wook Kim,
Sung-Mo Kang:
Energy-efficient skewed static logic with dual Vt: design and synthesis.
IEEE Trans. VLSI Syst. 11(1): 64-70 (2003) |
| 114 | | Ki-Wook Kim,
Seong-Ook Jung,
Unni Narayanan,
C. L. Liu,
Sung-Mo Kang:
Noise-aware interconnect power optimization in domino logic synthesis.
IEEE Trans. VLSI Syst. 11(1): 79-89 (2003) |
| 113 | | Jaesik Lee,
Ki-Wook Kim,
Yoonjong Huh,
Peter Bendix,
Sung-Mo Kang:
Chip-level charged-device modeling and simulation in CMOS integrated circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 67-81 (2003) |
| 112 | | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Timing constraints for domino logic gates with timing-dependent keepers.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 96-103 (2003) |
| 2002 |
|---|
| 111 | | Robert K. Grube,
Qi Wang,
Sung-Mo Kang:
Design limitations in deep sub-0.1µm CMOS SRAM.
ACM Great Lakes Symposium on VLSI 2002: 94-97 |
| 110 | | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Low-swing clock domino logic incorporating dual supply and dual threshold voltages.
DAC 2002: 467-472 |
| 109 | | Jaesik Lee,
Ki-Wook Kim,
Sung-Mo Kang:
VeriCDF: a new verification methodology for charged device failures.
DAC 2002: 874-879 |
| 108 | | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain.
DATE 2002: 260-267 |
| 107 | | Kwang-Hyun Baek,
Myung-Jun Choe,
Sung-Mo Kang:
A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance.
ISCAS (5) 2002: 53-56 |
| 106 | | Sung-Mo Kang:
On-chip thermal engineering for peta-scale integration.
ISPD 2002: 76-76 |
| 105 | | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Optimal Timing for Skew-Tolerant High-Speed Domino Logic.
ISVLSI 2002: 41-46 |
| 104 | | Ki-Wook Kim,
Taewhan Kim,
TingTing Hwang,
Sung-Mo Kang,
C. L. Liu:
Logic transformation for low-power synthesis.
ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002) |
| 103 | | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Noise constrained transistor sizing and power optimization for dual Vst domino logic.
IEEE Trans. VLSI Syst. 10(5): 532-541 (2002) |
| 102 | | Ki-Wook Kim,
Taewhan Kim,
C. L. Liu,
Sung-Mo Kang:
Domino logic synthesis based on implication graph.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 232-240 (2002) |
| 2001 |
|---|
| 101 | | Kaushik Roy,
Sung-Mo Kang,
Cheng-Kok Koh:
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001
ACM 2001 |
| 100 | | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Transistor sizing for reliable domino logic design in dual threshold voltage technologies.
ACM Great Lakes Symposium on VLSI 2001: 133-138 |
| 99 | | Edward Ahn,
Seung-Moon Yoo,
Sung-Mo Kang:
Effective algorithms for cache-level compression.
ACM Great Lakes Symposium on VLSI 2001: 89-92 |
| 98 | | Seung-Moon Yoo,
Seong-Ook Jung,
Sung-Mo Kang:
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test.
ACM Great Lakes Symposium on VLSI 2001: 93-96 |
| 97 | | Ki-Wook Kim,
Seong-Ook Jung,
Prashant Saxena,
C. L. Liu,
Sung-Mo Kang:
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.
DAC 2001: 732-737 |
| 96 | | Jaesik Lee,
Yoonjong Huh,
Peter Bendix,
Sung-Mo Kang:
Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems.
ICCD 2001: 406-414 |
| 95 | | Jinghong Chen,
Sung-Mo Kang:
Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition.
ISCAS (3) 2001: 457-460 |
| 94 | | Seung-Moon Yoo,
Seong-Ook Jung,
Sung-Mo Kang:
Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT.
ISCAS (4) 2001: 1-4 |
| 93 | | Seong-Ook Jung,
Seung-Moon Yoo,
Ki-Wook Kim,
Sung-Mo Kang:
Skew-tolerant high-speed (STHS) domino logic.
ISCAS (4) 2001: 154-157 |
| 92 | | Seong-Ook Jung,
Ki-Wook Kim,
Sung-Mo Kang:
Noise constrained power optimization for dual VT domino logic.
ISCAS (4) 2001: 158-161 |
| 91 | | Jaesik Lee,
Yoonjong Huh,
Peter Bendix,
Sung-Mo Kang:
Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology.
ISCAS (4) 2001: 746-749 |
| 90 | | Chulwoo Kim,
Sung-Mo Kang:
A low-power reduced swing single clock flip-flop.
ISCAS (4) 2001: 806-809 |
| 89 | | Chulwoo Kim,
Ki-Wook Kim,
Sung-Mo Kang:
Energy-efficient skewed static logic design with dual Vt.
ISCAS (4) 2001: 882-885 |
| 88 | | Seung-Moon Yoo,
Chulwoo Kim,
Seong-Ook Jung,
Kwang-Hyun Baek,
Sung-Mo Kang:
New current-mode sense amplifiers for high density DRAM and PIM architectures.
ISCAS (4) 2001: 938-941 |
| 87 | | Ki-Wook Kim,
Seong-Ook Jung,
Sung-Mo Kang:
Coupling-aware minimum delay optimization for domino logic circuits.
ISCAS (5) 2001: 371-374 |
| 86 | | Q. Li,
Sung-Mo Kang:
Trapezoid-to-simple polygon recomposition for resistance extraction.
ISCAS (5) 2001: 495-498 |
| 85 | | Q. Li,
Yoonjong Huh,
Jau-Wen Chen,
Peter Bendix,
Sung-Mo Kang:
ESD design rule checker.
ISCAS (5) 2001: 499-502 |
| 84 | | Q. Li,
Yoonjong Huh,
Jau-Wen Chen,
Peter Bendix,
Sung-Mo Kang:
Full chip ESD design rule checking.
ISCAS (5) 2001: 503-506 |
| 83 | | Ki-Wook Kim,
Sung-Mo Kang:
Crosstalk noise minimization in domino logic design.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1091-1100 (2001) |
| 2000 |
|---|
| 82 | | Qiao Li,
Sung-Mo Kang:
Technology independent arbitrary device extractor.
ACM Great Lakes Symposium on VLSI 2000: 143-146 |
| 81 | | Qiao Li,
Sung-Mo Kang:
Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching.
ACM Great Lakes Symposium on VLSI 2000: 183-188 |
| 80 | | Ki-Wook Kim,
Unni Narayanan,
Sung-Mo Kang:
Domino logic synthesis minimizing crosstalk.
DAC 2000: 280-285 |
| 79 | | N. S. Nagaraj,
Andrzej J. Strojwas,
Sani R. Nassif,
Ray Hokinson,
Tak Young,
Wonjae L. Kang,
David Overhauser,
Sung-Mo Kang:
When bad things happen to good chips (panel session).
DAC 2000: 736-737 |
| 78 | | Ching-Han Tsai,
Sung-Mo Kang:
Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction.
DAC 2000: 750-755 |
| 77 | | Ki-Wook Kim,
Kwang-Hyun Baek,
Naresh R. Shanbhag,
C. L. Liu,
Sung-Mo Kang:
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design.
ICCAD 2000: 318-321 |
| 76 | | Chulwoo Kim,
Jaesik Lee,
Kwang-Hyun Baek,
Eric Martina,
Sung-Mo Kang:
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology.
ICCD 2000: 59-64 |
| 75 | | Ki-Wook Kim,
Seong-Ook Jung,
Unni Narayanan,
C. L. Liu,
Sung-Mo Kang:
Noise-aware power optimization for on-chip interconnect.
ISLPED 2000: 108-113 |
| 74 | | Jay R. Moorman,
John W. Lockwood,
Sung-Mo Kang:
Real-time prioritized call admission control in a base station scheduler.
WOWMOM 2000: 28-37 |
| 73 | | Yi-Kan Cheng,
Sung-Mo Kang:
A temperature-aware simulation environment for reliable ULSI chipdesign.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1211-1220 (2000) |
| 72 | | Danqing Chen,
Erhong Li,
Elyse Rosenbaum,
Sung-Mo Kang:
Interconnect thermal modeling for accurate simulation of circuittiming and reliability.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 197-205 (2000) |
| 71 | | Ching-Han Tsai,
Sung-Mo Kang:
Cell-level placement for improving substrate thermal distribution.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 253-266 (2000) |
| 1999 |
|---|
| 70 | | Tong Li,
Ching-Han Tsai,
Elyse Rosenbaum,
Sung-Mo Kang:
Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation.
DAC 1999: 549-554 |
| 69 | | Ki-Wook Kim,
Sung-Mo Kang,
TingTing Hwang,
C. L. Liu:
Logic Transformation for Low Power Synthesis.
DATE 1999: 158-162 |
| 68 | | Seung-Moon Yoo,
Sung-Mo Kang:
No-Race Charge-Recycling Differential Logic (NCDL).
Great Lakes Symposium on VLSI 1999: 202-205 |
| 67 | | Chulwoo Kim,
Seung-Moon Yoo,
Sung-Mo Kang:
NMOS Energy Recovery Logic.
Great Lakes Symposium on VLSI 1999: 310-313 |
| 66 | | Ki-Wook Kim,
C. L. Liu,
Sung-Mo Kang:
Implication graph based domino logic synthesis.
ICCAD 1999: 111-114 |
| 65 | | Yi-Kan Cheng,
Sung-Mo Kang:
An efficient method for hot-spot identification in ULSI circuits.
ICCAD 1999: 124-127 |
| 64 | | Seung-Moon Yoo,
Sung-Mo Kang:
CMOS Pass-gate No-race Charge-recycling Logic (CPNCL).
ISCAS (1) 1999: 226-229 |
| 63 | | Jinghong Chen,
Sung-Mo Kang:
A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits.
ISCAS (6) 1999: 194-197 |
| 62 | | Yi-Kan Cheng,
Sung-Mo Kang:
Temperature-driven power and timing analysis for CMOS ULSI circuits.
ISCAS (6) 1999: 214-217 |
| 61 | | Ching-Han Tsai,
Sung-Mo Kang:
Macrocell placement with temperature profile optimization.
ISCAS (6) 1999: 390-393 |
| 60 | | Danqing Chen,
Erhong Li,
Elyse Rosenbaum,
Sung-Mo Kang:
Interconnect thermal modeling for determining design limits on current density.
ISPD 1999: 172-178 |
| 59 | | Ching-Han Tsai,
Sung-Mo Kang:
Standard cell placement for even on-chip thermal distribution.
ISPD 1999: 179-184 |
| 1998 |
|---|
| 58 | | Tong Li,
Sung-Mo Kang:
Layout Extraction and Verification Methodology CMOS I/O Circuits.
DAC 1998: 291-296 |
| 57 | | Tong Li,
Ching-Han Tsai,
Sung-Mo Kang:
Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress.
ICCAD 1998: 6-11 |
| 56 | | Li-Pen Yuan,
Chin-Chi Teng,
Sung-Mo Kang:
Statistical estimation of average power dissipation using nonparametric techniques.
IEEE Trans. VLSI Syst. 6(1): 65-73 (1998) |
| 55 | | Yi-Kan Cheng,
Prasun Raha,
Chin-Chi Teng,
Elyse Rosenbaum,
Sung-Mo Kang:
ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 668-681 (1998) |
| 1997 |
|---|
| 54 | | Li-Pen Yuan,
Chin-Chi Teng,
Sung-Mo Kang:
Statistical Estimation of Average Power Dissipation in Sequential Circuits.
DAC 1997: 377-382 |
| 53 | | Jaewon Kim,
Sung-Mo Kang:
An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design.
DAC 1997: 456-459 |
| 52 | | Sueng-Yong Park,
Vaduvur Bharghavan,
Sung-Mo Kang:
Data Link Level Support for Handoff in Wireless ATM Network.
ICC (2) 1997: 765-769 |
| 51 | | Ashfaq Hossain,
Sung-Mo Kang,
Bob Horst:
Performance Comparison of Video Transport over ATM and ServerNet Interconnects.
ICMCS 1997: 612-613 |
| 50 | | Haoran Duan,
John W. Lockwood,
Sung-Mo Kang,
J. D. Will:
A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches.
INFOCOM 1997: 20-28 |
| 49 | | Li-Pen Yuan,
Sung-Mo Kang:
A sequential procedure for average power analysis of sequential circuits.
ISLPED 1997: 231-234 |
| 48 | | Brent K. Whitlock,
Petar K. Pepeljugoski,
Daniel M. Kuchta,
John D. Crow,
Sung-Mo Kang:
Computer Modeling and Simulation of the Optoelectronic Technology Consortium (OETC) Optical Bus.
IEEE Journal on Selected Areas in Communications 15(4): 717-730 (1997) |
| 47 | | Chin-Chi Teng,
Yi-Kan Cheng,
Elyse Rosenbaum,
Sung-Mo Kang:
iTEM: a temperature-dependent electromigration reliability diagnosis tool.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 882-893 (1997) |
| 1996 |
|---|
| 46 | | Yi-Kan Cheng,
Chin-Chi Teng,
Abhijit Dharchoudhury,
Elyse Rosenbaum,
Sung-Mo Kang:
iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips.
DAC 1996: 548-551 |
| 45 | | Chin-Chi Teng,
Yi-Kan Cheng,
Elyse Rosenbaum,
Sung-Mo Kang:
Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects.
DAC 1996: 752-757 |
| 44 | | Li-Pen Yuan,
Chin-Chi Teng,
Sung-Mo Kang:
Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques.
ISLPED 1996: 73-78 |
| 43 | | Anthony M. Hill,
Sung-Mo Kang:
Determining accuracy bounds for simulation-based switching activity estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 611-618 (1996) |
| 42 | | Jaewon Kim,
Sung-Mo Kang:
A new triple-layer OTC channel router.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1059-1070 (1996) |
| 1995 |
|---|
| 41 | | Tanay Karnik,
Sung-Mo Kang:
An empirical model for accurate estimation of routing delay in FPGAs.
ICCAD 1995: 328-331 |
| 40 | | Chin-Chi Teng,
Anthony M. Hill,
Sung-Mo Kang:
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits.
ICCAD 1995: 366-370 |
| 39 | | Jaewon Kim,
Sung-Mo Kang:
A timing-driven data path layout synthesis with integer programming.
ICCAD 1995: 716-719 |
| 38 | | Yi-Kan Cheng,
Sung-Mo Kang:
Chip-Level Thermal Simulator to Predict VLSI Chip Temperature.
ISCAS 1995: 1392-1395 |
| 37 | | Elizabeth J. Brauer,
Sung-Mo Kang:
An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations.
ISCAS 1995: 1580-1583 |
| 36 | | Myong H. Cynn,
Sung-Mo Kang:
Incremental Node Extraction Algorithms for Incremental Layout System.
ISCAS 1995: 1691-1694 |
| 35 | | Elizabeth J. Brauer,
Sung-Mo Kang:
Estimating Node Voltages in Bipolar Circuits Using Linear Programming.
ISCAS 1995: 901-903 |
| 34 | | Anthony M. Hill,
Sung-Mo Kang:
Determining accuracy bounds for simulation-based switching activity estimation.
ISLPD 1995: 215-220 |
| 33 | | Elizabeth J. Brauer,
Sung-Mo Kang:
An algorithm for functional verification of digital ECL circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1546-1556 (1995) |
| 32 | | Abhijit Dharchoudhury,
Sung-Mo Kang:
Worst-case analysis and optimization of VLSI circuit performances.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 481-492 (1995) |
| 31 | | Mysore Sriram,
Sung-Mo Kang:
Efficient approximation of the time domain response of lossy coupled transmission line trees.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 1013-1024 (1995) |
| 1994 |
|---|
| 30 | | Abhijit Dharchoudhury,
Sung-Mo Kang,
K. H. (Kane) Kim,
S. H. Lee:
Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics.
ICCAD 1994: 190-194 |
| 29 | | Abhijit Dharchoudhury,
Sung-Mo Kang,
Hungse Cha,
Janak H. Patel:
Fast timing simulation of transient faults in digital circuits.
ICCAD 1994: 719-722 |
| 28 | | Eby G. Friedman,
Sung-Mo Kang,
Eric A. Vittoz,
David J. Allstot,
Erik P. Harris,
Ran-Hong Yan:
Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS.
ISCAS 1994: 1-6 |
| 27 | | Jaewon Kim,
Sung-Mo Kang,
Sachin S. Sapatnekar:
High Performance CMOS Macromodule Layout Synthesis.
ISCAS 1994: 179-182 |
| 26 | | Anthony M. Hill,
Sung-Mo Kang:
Genetic Algorithm Based Design Optimization Of CMOS VLSI Circuits.
PPSN 1994: 546-555 |
| 25 | | Sachin S. Sapatnekar,
Pravin M. Vaidya,
Sung-Mo Kang:
Convexity-based algorithms for design centering.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1536-1549 (1994) |
| 24 | | Carlos H. Díaz,
Sung-Mo Kang,
Charvaka Duvvury:
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 482-493 (1994) |
| 1993 |
|---|
| 23 | | Abhijit Dharchoudhury,
Sung-Mo Kang:
Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits.
DAC 1993: 154-158 |
| 22 | | Mysore Sriram,
Sung-Mo Kang:
Fast Approximation of the Transient Response of Lossy Transmision Line Trees.
DAC 1993: 691-696 |
| 21 | | Carlos H. Díaz,
Charvaka Duvvury,
Sung-Mo Kang:
Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices.
ISCAS 1993: 1389-1392 |
| 20 | | Elizabeth J. Brauer,
Sung-Mo Kang:
Functional Verification of ECL Circuits Including Voltage Regulators.
ISCAS 1993: 1710-1713 |
| 19 | | Sachin S. Sapatnekar,
Pravin M. Vaidya,
Sung-Mo Kang:
Feasible Region Approximation Using Convex Polytopes.
ISCAS 1993: 1786-1789 |
| 18 | | Jun Dong Cho,
Majid Sarrafzadeh,
Mysore Sriram,
Sung-Mo Kang:
High-Performance MCM Routing.
IEEE Design & Test of Computers 10(4): 27-37 (1993) |
| 17 | | Sachin S. Sapatnekar,
Vasant B. Rao,
Pravin M. Vaidya,
Sung-Mo Kang:
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1621-1634 (1993) |
| 16 | | Yung-Ho Shih,
Yusuf Leblebici,
Sung-Mo Kang:
ILLIADS: a fast timing and reliability simulator for digital MOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1387-1402 (1993) |
| 1992 |
|---|
| 15 | | Abhijit Dharchoudhury,
Sung-Mo Kang:
An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits.
DAC 1992: 704-709 |
| 14 | | Mysore Sriram,
Sung-Mo Kang:
Detailed layer assignment for MCM routing.
ICCAD 1992: 386-389 |
| 13 | | Carlos H. Díaz,
Sung-Mo Kang:
New algorithms for circuit simulation of device breakdown.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(11): 1344-1354 (1992) |
| 12 | | Richard W. Thaik,
Ngee Lek,
Sung-Mo Kang:
A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(12): 1479-1494 (1992) |
| 11 | | Yusuf Leblebici,
Sung-Mo Kang:
Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 235-246 (1992) |
| 10 | | Yung-Ho Shih,
Sung-Mo Kang:
Analytic transient solution of general MOS circuit primitives.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 719-731 (1992) |
| 1991 |
|---|
| 9 | | Yung-Ho Shih,
Sung-Mo Kang:
ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach.
DAC 1991: 20-25 |
| 8 | | Yung-Ho Shih,
Yusuf Leblebici,
Sung-Mo Kang:
New Simulation Methods for MOS VLSI Timing and Reliability.
ICCAD 1991: 162-165 |
| 7 | | Carlos H. Díaz,
Sung-Mo Kang,
Yusuf Leblebici:
An accurate analytical delay model for BiCMOS driver circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 577-588 (1991) |
| 6 | | H. Y. Chen,
Sung-Mo Kang:
A new circuit optimization technique for high performance CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 670-677 (1991) |
| 1990 |
|---|
| 5 | | Yusuf Leblebici,
Sung-Mo Kang:
An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis.
ICCAD 1990: 400-403 |
| 1987 |
|---|
| 4 | | D. K. Hwang,
W. Kent Fuchs,
Sung-Mo Kang:
An Efficient Approach to Gate Matrix Layout.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 802-809 (1987) |
| 3 | | Sung-Mo Kang:
Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 886-891 (1987) |
| 2 | | Tat-Kwan Yu,
Sung-Mo Kang,
I. N. Haji,
Timothy N. Trick:
Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 1013-1022 (1987) |
| 1983 |
|---|
| 1 | | Sung-Mo Kang,
Robert H. Krambeck,
Hung-Fai Stephen Law,
Alexander D. Lopez:
Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(1): 18-29 (1983) |
