 | 2004 |
|---|
| 15 |       | Nick Kanopoulos:
Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization.
PATMOS 2004: 2 |
| 1998 |
|---|
| 14 | | K. Adaos,
George Alexiou,
Nick Kanopoulos:
An Extensible, Low Cost Rapid Prototyping Environment Based on a Reconfigurable Set of FPGAs.
International Workshop on Rapid System Prototyping 1998: 78-83 |
| 1995 |
|---|
| 13 | | Jason P. Hurst,
Nick Kanopoulos:
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.
Asian Test Symposium 1995: 346-352 |
| 12 | | Theodore Karoubalis,
George Alexiou,
Nick Kanopoulos:
Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs).
EURO-DAC 1995: 282-287 |
| 11 |  | Apostolos Dollas,
Nick Kanopoulos:
Reducing the Time to Market Through Rapid Prototyping - Guest Editors' Introduction.
IEEE Computer 28(2): 14-15 (1995) |
| 1994 |
|---|
| 10 | | George Alexiou,
Dimitrios Stiliadis,
Nick Kanopoulos:
Design and Implementation of a High-Performance, Modular, Sorting Engine.
EDAC-ETC-EUROASIC 1994: 2-8 |
| 9 | | Tassos Markas,
Mark Royals,
Nick Kanopoulos:
Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations.
IEEE Trans. VLSI Syst. 2(2): 149-156 (1994) |
| 8 | | Theodoros Antonakopoulos,
Nick Kanopoulos:
Multiple boundary scan-paths for minimizing circuit-board test-application time.
Microprocessing and Microprogramming 40(6): 377-386 (1994) |
| 1993 |
|---|
| 7 | | Nazar S. Haider,
Nick Kanopoulos:
Efficient board interconnect testing using the split boundary scan register.
J. Electronic Testing 4(2): 181-189 (1993) |
| 1992 |
|---|
| 6 | | Nick Kanopoulos,
Dimitris Pantzartzis,
Frederick R. Bartram:
Design of Self-Checking Circuits Using DCVS Logic: A Case Study.
IEEE Trans. Computers 41(7): 891-896 (1992) |
| 1990 |
|---|
| 5 | | Tassos Markas,
Mark Royals,
Nick Kanopoulos:
On Distributed Fault Simulation.
IEEE Computer 23(1): 40-52 (1990) |
| 1989 |
|---|
| 4 | | Jill J. Hallenbeck,
James R. Cybrynski,
Nick Kanopoulos,
Tassos Markas,
Nagesh Vasanthavada:
The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability.
IEEE Computer 22(4): 59-68 (1989) |
| 1988 |
|---|
| 3 | | Jill J. Hallenbeck,
Nick Kanopoulos,
Nagesh Vasanthavada,
James W. Watterson:
CAD Tools for Supporting System Design for Testability.
ITC 1988: 993 |
| 1986 |
|---|
| 2 | | Nick Kanopoulos,
Peter N. Marinos:
A High-Performance Single-Chip VLSI Signal Processor Architecture.
Aegean Workshop on Computing 1986: 166-179 |
| 1983 |
|---|
| 1 | | Nick Kanopoulos,
G. T. Mitchell:
Testing of Bit-Serial Signal Processors.
ITC 1983: 719-727 |
