Chi-Chou Kao

	2007
5		Chi-Chou Kao: A High Flexibility Design for Clock Distribution Network in System on Chip. Journal of Circuits, Systems, and Computers 16(1): 51-63 (2007)
	2005
4		Chi-Chou Kao, Yen-Tai Lai: An efficient algorithm for finding the minimal-area FPGA technology mapping. ACM Trans. Design Autom. Electr. Syst. 10(1): 168-186 (2005)
	2004
3		Chi-Chou Kao, Yen-Tai Lai: Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction. ASP-DAC 2004: 719-724
	1999
2		Chi-Chou Kao, Yen-Tai Lai: A routability and performance driven technology mapping algorithm for LUT based FPGA designs. ISCAS (1) 1999: 474-477
1		Yen-Tai Lai, Chi-Chou Kao, Wu-Chien Shieh: A quadratic programming method for interconnection crosstalk minimization. ISCAS (6) 1999: 270-273

Coauthor Index

1	Yen-Tai Lai	[1] [2] [3] [4]
2	Wu-Chien Shieh	[1]