 | 2007 |
|---|
| 8 |       | Hemangee K. Kapoor:
Modelling Latency-Insensitive Systems in CSP.
ACSD 2007: 231-232 |
| 7 | | Mark B. Josephs,
Hemangee K. Kapoor:
Controllable Delay-Insensitive Processes.
Fundam. Inform. 78(1): 101-130 (2007) |
| 2006 |
|---|
| 6 | | Hemangee K. Kapoor:
Formal Modelling and Verification of an Asynchronous DLX Pipeline.
SEFM 2006: 118-127 |
| 5 | | Hemangee K. Kapoor,
Mark B. Josephs,
Dennis P. Furey:
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments.
Fundam. Inform. 70(1-2): 21-48 (2006) |
| 2005 |
|---|
| 4 | | Hemangee K. Kapoor,
Mark B. Josephs:
Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation.
ACSD 2005: 58-67 |
| 2004 |
|---|
| 3 | | Hemangee K. Kapoor,
Mark B. Josephs,
Dennis P. Furey:
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments.
ACSD 2004: 89-98 |
| 2 | | Hemangee K. Kapoor,
Mark B. Josephs:
Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis.
DAC 2004: 830-833 |
| 1 | | Hemangee K. Kapoor,
Mark B. Josephs:
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench.
Inf. Process. Lett. 89(6): 293-296 (2004) |
